• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 A
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• pp.169-171
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• 2002

The western route of KEPCO's 765kV transmission line has been tentatively operating as 345kV voltage before commercial operation. After finishing the test operation of 765kV substation in 2002. KEPCO decided to operate the 765kV line for commercial operation. During the applying of 765kV voltage to the transmission line, double circuit transmission line will be operated with two voltage grades of 765kV and 345kV. Because the earthing switch is installed on both end of transmission line, we had estimated the electrostatic induction voltage and electromagnetic induction current before the line energizing in order to confirm the ratings of earthing switch. The induced voltage and current is very important for the maintenance of parallel circuit. This paper describes the simulation study of electrical phenomena such as electrostatic induction voltage from the parallel line and electromagnetic induction current from the parallel circuit. The transmission line model was developed by EMTP (Electro-Magnetic Transient Program).

• 한국전자파학회논문지
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• 제19권7호
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• pp.761-770
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• 2008

임피던스 인버터 및 어드미턴스 인버터는 마이크로파 여파기 설계에 자주 사용되는 개념적인 소자이다. 본 논문에서는 일반적 무 손실 2-포트 회로의 인버터를 사용한 등가회로를 제시하였다 이 방법은 기존의 방법과 달리 무손실 2-포트 회로의 z- 또는 y-파라미터를 알 경우, 이를 이용하여 용이하게 나타낼 수 있다. 이 방법을 평행 결합 선로(parallel coupled line) 및 비평행 결한 선로(anti-parallel coupled line)에 적용하고, 기존의 등가회로에 대하여 비교 검토하였다. 또한, 마이크로스트립 평행 결합 선로 여파기는 설계된 여파기에 대해 주파수 응답의 왜곡을 발생시키게 되는데, 이를 보상하기 위하여 알려진 기존 결과들과 본 논문의 유도 결과를 비교 검토하였다. 평행 결합 선로 여파기 설계시 제시된 등가회로는 기존 등가회로와의 차이로 여파기 설계에 특이성을 보이게 된다. 본 논문에서는 제시된 등가회로에 대하여 설계 방법을 제시하고, 기존의 연구 결과와 비교하여 제시된 방법이 보다 정확한 결과를 주는 것을 보였다.

• 대한전기학회논문지:전력기술부문A
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• 제52권1호
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• pp.29-35
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• 2003

This paper presents a fault location algorithm when there are parallel circuits in power system networks. In transmission networks, a fault location method using the distribution factor of fault currents is introduced and in distribution networks a method using direct 3-phase circuit analysis is developed, because the distribution networks are unbalanced. The effect of parallel circuits in fault location is studied in this paper. The effect is important for the range of protecting zones of distance relay in transmission networks and fault location in distribution networks. The result of developed fault location algorithm shows high accuracy in the simulation that using the EMTP.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권11호
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• pp.577-582
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• 2004

In this paper, lumped equivalent circuits for a conventional parallel directional coupler are proposed. This equivalent circuits only have self inductance and self capacitance, so we can design exact lumped equivalent circuit. The equivalent circuit and design formula for the presented lumped element coupler is derived based on the even- and odd-mode properties of parallel-coupled line. By using the derived design formula, we have designed the 3dB and 4.7dB MMIC couplers at the center frequency of 3.4GHz and 5.6GHz respectively. Measurements for the designed MMIC directional couplers show at 4dB and 5.2dB-coupling value at the center frequency of 3.4GHz and 5.6GHz. Excellent agreements between simulation results and measurement results on the designed directional couplers show the validity of this paper

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.726-732
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• 2014

A current flowing through a distribution conductor produces induced voltage, which is harmful to a telecommunication line. Previous research on induced voltage has been focused on single-circuit lines in the distribution system. However, the double-circuit lines, referred to as parallel distribution lines, are widely used in distribution systems because they have significant economic and environmental advantages over single-circuit lines. Therefore, a study on the induced voltage in double-circuit lines is needed. This paper presents a method of calculating the induced voltage in a parallel distribution system using four-terminal parameters and vector analysis. The calculation method is verified by the Electromagnetic Transient Program (EMTP) simulation.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권9호
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• pp.531-538
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• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• 한국전자파학회논문지
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• 제16권1호
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• pp.78-83
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• 2005

본 논문에서는 적층 Inter-digital 공진기를 이용한 LTCC 대역통과 여파기의 등가회로를 제안하고, 2.4 GHz 대역의 여파기 설계에 적용하였다. 본 논문의 LTCC 적층 칩 대역통과 여파기는 평면상에서는 Comb-line 구조이고 단면상에서는 Inter-digital 구조로 구성된다. Comb-line 구조와 Inter-digital 구조의 평행 결합선로의 등가회로를 본 논문의 여파기에 적용하여 여파기 전체의 등가회로를 구성하였다. 이 등가회로는 공진기 사이의 결합 구조가 다중의 결합 구조를 갖는다. 이를 하나의 결합 구조로 통합하여 인버터를 이용한 대역통과 여파기의 설계방법을 적용하였다. 2.4 GHz 대역에서 3단의 대역통과 여파기를 설계, 제작하였다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.153-156
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• 2002

In this paper, we have designed a small size lumped/distributed hybrid element directional coupler using parallel coupled-line theory. a hybrid lumped equivalent circuit for a conventional parallel directional coupler is proposed. The equivalent circuit and design formula for the presented lumped element coupler are derived based on the even- and odd-mode properties of a parallel-coupled line. By using the derived design formula, we have extracted design parameters and designed the 3㏈ and 10㏈ small size lumped element directional couplers at the center frequency of 2Ghz. Excellent agreements between design theory and simulation on the designed directional couplers show the validity of this paper.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 A
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• pp.282-284
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• 1999

This paper presents an accurate algorithm for fault location of a single phase to earth fault on a two-parallel transmission line using only one-terminal data. It is impossible to calculate the accurate fault distance, because of the unknown fault resistance and fault current at the fault point. The faulted line circuit and the zero-sequence circuit of two-parallel line are used as a fault location model, which the source impedance of the remote end is not involved. The algorithm can eliminate the effect of load flow and the fault resistance in calculating the fault location.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 A
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• pp.49-51
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• 2000

This paper presents a fault location algorithm for single-phase-to-ground faults on the teed circuit of a parallel transmission line. This algorithm uses only local end voltage and current information. Remote end and fault currents are calculated by using distribution factors. To reduce load current effect, negative sequence current is used. EMTP simulation result have shown effectiveness of the algorithm under various conditions.