• 전자공학회논문지
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• 제54권6호
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• pp.55-64
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• 2017

대용량 고화질의 영상 응용분야에서는 많은 양의 데이터를 고속으로 처리하는 기술이 필요하며, 이를 위해 고속화된 병렬처리 시스템이 요구된다. 2004년 park은 병렬처리 메모리의 충돌 없이 여러 처리기에 데이터를 접속할 수 있는 방법을 제안하였다. 제안된 MAMS(Multi-Access Memory System) 는 이후 MAMS-PP16 및 MAMS-PP64 등으로 추가적인 연구가 이루어졌다. MAMS는 병렬처리를 위한 메모리 아키텍처로써 One-chip으로 구성되어야하기 때문에 기존 MAMS와 동일한 기능을 수행하면서 아키텍처의 최소화 하는 방법의 연구가 필요하다. 주소 계산 (ACR : Address Calculation and Routing) circuit과 MMS(Memory Module Selection)circuit의 아키텍처는 메모리에 있는 데이터를 병렬처리기(Prossing Elements)들에게 전달한다. 본 논문에서는 MMS circuit을 사용하지 않고 ACR circuit 내부에 1개의 쉬프트와 메모리 모듈의 개수만큼의 조건문으로 구성하는 방법을 통해 아키텍처를 최소화 하는 방법을 제안한다. 구현한 아키텍처의 검증을 위해 Image correlation 실험을 하였다. 실험을 통하여 제안된 MAMS-PP64의 처리시간을 측정 하였으며, 그 결과 Ratio가 평균 1.05향상 된 결과를 확인 할 수 있었다.

• IEIE Transactions on Smart Processing and Computing
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• 제6권2호
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• pp.133-139
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• 2017

Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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• pp.285-288
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• 2005

We propose a novel programmable miniature vision module based on a custom designed analog VLSI (aVLSI) chip. The vision module consists of the optical flow vision sensor embedded with commercial off-the-shelves digital hardware; in our case is the Intel XScale PXA270 processor enforced with a programmable gate array device. The aVLSI sensor provides gray-scale imager data as well as smooth optical flow estimates, thus each pixel gives a triplet of information that can be continuously read out as three independent images. The particular computational architecture of the custom designed sensor, which is fully parallel and also analog, allows for efficient real-time estimations of the smooth optical flow. The Intel XScale PXA270 controls the sensor read-out and furthermore allows, together with the programmable gate array, for additional higher level processing of the intensity image and optical flow data. It also provides the necessary standard interface such that the module can be easily programmed and integrated into different vision systems, or even form a complete stand-alone vision system itself. The low power consumption, small size and flexible interface of the proposed vision module suggests that it could be particularly well suited as a vision system in an autonomous robotics platform and especially well suited for educational projects in the robotic sciences.

• 한국통신학회논문지
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• 제21권11호
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• pp.2739-2749
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• 1996

This aper introduces the multiple Neocognitron module approach for the effective target reognition. The Neocognitron which is designed to classify a pattern by extracting the local features from it, seems to be an unique method that can perform a pattern recognition using the neural networks. But due to its rigid structure, the Neocognitron must be reconstructed whenever there exists a variation on the number of classes. This is a quite difficult problem for the target recognition application that needs huge amount of computation and numerous classes to be classified. In this paper, we construct several smaller Necognitrom modules and train each module to adapt each class. After construction of the mulules, we integrate them in parallel so as to adaopt input at the same time and to produce each score that shold be matched to be learned class. This approach can reduce the sizes of the networks and is adaptive to the increase of classes as well as the authentic distortion, shift, scale variation and slight rotation invariant properties of general Neocognitron. This paper show the effectiveness of the proposed approach through some experience and performs analysis of the inhibitory interconnections in the architecture of the multiple module structure.

• 전력전자학회논문지
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• 제26권1호
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• pp.38-45
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• 2021

The photovoltaic module has the characteristic of changing its output characteristics depending on the amount of radiation and temperature, where the arrays that connect them in series and parallel also have the same characteristics. These characteristics require the MPPT technique to find the maximum power point. Existing P&O and IncCond cannot find the global maximum power point (GMPP) for partial shading. Moreover, in the case of Improved-GMPPT and Enhanced Search-Skip-Judge-GMPPT, GMPP due to partial shading can be found, but the variation in the open voltage during temperature fluctuations will affect the operation of the Skip and will not be able to perform accurate MPPT operation. In this study, we analyzed the correlation between voltage, current, and power under solar module and array conditions. We also proposed a technique to find the maximum power point even for temperature fluctuations using not only the amount of radiation but also the temperature coefficient. The proposed control technique was verified through simulations and experiments by constructing a 2.5 kW single-phase solar power generation system.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 추계학술대회 논문집
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• pp.299-303
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• 2004

In our pervious paper, a new parallel-type spherical 3-degree-of-freedom mechanism consisting of a two-degree-of-freedom parallel module and a serial RRR subchain was proposed[1]. In this paper, its improved version is suggested and implemented. Differently from the previous 3-dof spherical mechanism, gear chains are incorporated into the current version of the mechanism to drive the distal revolute joint of the serial subchain from the base of the mechanism and in fact, the modification significantly improves kinematic characteristics of the mechanism within its workspace. Firstly, after a brief description on its structure, the closed-form solutions of both the forward and the reverse position analysis are derived. Secondly, the first-order kinematic model of the mechanism for the inputs which are assumed to be located at the base is derived. Thirdly, through the simulations of the kinematic analysis via. kinematic isotropic index, it is confirmed that the mechanism has much more improved isotropic properties throughout the workspace of the mechanism than the previous mechanism in [1]. Lastly, the proposed mechanism is implemented to verify the results from this analysis.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제15권10호
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• pp.3729-3749
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• 2021

At present, deep convolution network-based salient object detection (SOD) has achieved impressive performance. However, it is still a challenging problem to make full use of the multi-scale information of the extracted features and which appropriate feature fusion method is adopted to process feature mapping. In this paper, we propose a new adjacency auxiliary network (AANet) based on multi-scale feature fusion for SOD. Firstly, we design the parallel connection feature enhancement module (PFEM) for each layer of feature extraction, which improves the feature density by connecting different dilated convolution branches in parallel, and add channel attention flow to fully extract the context information of features. Then the adjacent layer features with close degree of abstraction but different characteristic properties are fused through the adjacent auxiliary module (AAM) to eliminate the ambiguity and noise of the features. Besides, in order to refine the features effectively to get more accurate object boundaries, we design adjacency decoder (AAM_D) based on adjacency auxiliary module (AAM), which concatenates the features of adjacent layers, extracts their spatial attention, and then combines them with the output of AAM. The outputs of AAM_D features with semantic information and spatial detail obtained from each feature are used as salient prediction maps for multi-level feature joint supervising. Experiment results on six benchmark SOD datasets demonstrate that the proposed method outperforms similar previous methods.

• 한국멀티미디어학회논문지
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• 제14권11호
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• pp.1401-1408
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• 2011

본 논문에서는 영상처리용 16개의 처리기를 위한 다중접근기억장치(Multi-Access Memory System) 및 병렬처리기의 칩을 설계하였다. 다중접근기억장치는 병렬접근 메모리 시스템의 한 종류로서 영상의 픽셀 데이터값에 8가지 타입으로 동시 접근이 가능하다. 또한 일정한 간격을 두고 픽셀 데이터값에 접근하는 것이 가능하다. 다중접근기억장치가 내장된 병렬처리기는 실제로 2003년에 구현되어진 적이 있다. 하지만 고해상도 영상을 실시간으로 처리하기에는 그 성능이 미치지 못하였다. 이에 본 논문에서는 이전의 시스템의 메모리 모듈(Memory Module)과 처리기(Processing Element)를 추가 확장하여 보다 개선된 병렬처리 시스템을 설계하였다. 이 시스템은 이전의 시스템보다는 3배, 시리얼 시스템보다는 6배 빠른 속도로 모폴로지컬 클로징(Morphological closing) 알고리즘의 수행이 가능하다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.405-406
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• 2006

Recently, the flat display modules such as plasma or TFT-LCD employ thin crystallized panels which are normally weak to high level transient mechanical energy inputs. As a result, anti-shock performance is one of the most important design specifications for TFT-LCD modules. However, most of large display module designs are generated based on engineers own experiences. Also, a large-scale analysis to evaluate complex material and structural behaviors is one of interesting topic in diverse engineering and scientific fields. The utilization of massively parallel processors has also been a recent trend of high performance computing. The objective of this paper is to introduce a parallel process system which consists of general purpose finite element analysis solver as well as parallelized PC cluster. The parallel processing system is constructed using thirty-two processing elements and the finite element program is developed by adopting hierarchical domain decomposition method. In order to verify the efficiency of the established system, an impact analysis on thin and complex sub-parts of flat display modules is performed. The evaluation results showed a good agreement with the corresponding reference solutions, and thus, the parallel process system seems to be a useful tool fur the complex structural analysis such as IT related products.

• 한국산업융합학회 논문집
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• 제26권6_2호
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• pp.1097-1108
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• 2023

Recently, demand for technology for energy economy and stable supply is increasing due to the increase in power demand of loads. The amount of DC power generation using new and renewable energy is noticeably increasing, and the use of DC power supplies is also increasing due to the increase in electric vehicles and digital loads. During parallel operation to increase the capacity of the power converter, the module bus method or the method using Can communication and serial communication has significant difficulties in smooth operation due to communication time delay for information sharing. Synchronization of information sharing of each power converter is essential for smooth parallel operation, and minimization of communication time delay is urgently needed as a way to overcome this problem. In this paper, a new communication method using pulse width information is proposed as a communication method specialized for parallel operation of power converters to compensate for the disadvantage of communication transmission delay in the existing system. The proposed communication method has the advantage of being easily implemented using the PWM and Capture function of the microcomputer. In addition, the DC/DC converter for DC distribution was verified through simulation and experiment, and it has the advantage of easy capacity expansion when applied to parallel operation of various types of power converters as well as DC/DC converters.