• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.51-54
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• 2000

This paper describes the fixed-point DSP implementation of a CELP(code-excited linear prediction)-based speech coder. The effective realization methodologies to maximize the utilization of the DSP's architectural features, specifically Parallel movement and pipelining are also presented together with the implementation results targeted for the ITU-T standard G.723.1 using Motorola DSP56309. The operation of the implemented speech coder is verified using the test vectors offered by the standard as well as using the peripheral interface circuits designed for the coder's real-time operation.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1029-1032
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• 1998

In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

• Speech Sciences
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• v.7 no.2
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• pp.225-234
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• 2000

This paper describes the fixed-point DSP implementation of a CELP(Code-excited linear prediction)-based speech coder. The effective realization methodologies to maximize the utilization of the DSP's architectural features, specifically parallel movement and pipelining are also presented together with the implementation results targeted for the ITU-T standard G.723.1 using Motorola DSP56362. The operation of the implemented speech coder is verified using the test vectors offered by the standard as well as using the peripheral interface circuits designed for the coder's real-time operation.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.1
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• pp.26-35
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• 1997

In this paper, a VHDL implementation method for the internet protocol (IP) placed on top of ATM, so called IP over ATM, is presented. The proposed implementation method employs a parallel processing architecture to reduce the processing time and offers 155.52Mbps (STM-1) interface with the full-duplex mode for the ATM-based network. Furthermore, in order to minimize the search time for the table look-up, a LANCAM-based structure combining the routing table with the ATMARP table is proposed. The VHDL simulation results show that this proposed method can transmit (receive) at 155.52Mbps with delays of 48.5 clocks (29.5clocks).

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.944-953
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• 1990

This paper describes design and implementation of a real-time high-precision vision system for an automation of SMT(surface mounting technology ). Also, a part inspection algorithm which calculates the position and direction of SMD(surface mounted device) accurately and performs the ruling using those information are presented, and a parallel processing technique for implementing those algorithms is also described. For a real-time implementation of iage acquisition and processing, several hardware modules, namely, multi-functional A/D-D/A board, frame memory board are developed. Particularly, a PE (processing element) board which employs the DSP56001 DSP (digital signal processor) is developed for the purpose of concurrent processing of part inspection algorithms. A stand-alone vision system is built by integration of the developed hardware modules and related softwares.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.343-356
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• 1991

An efficient real-time implementation of digital filtering algorithms using a multiprocessor system in a ring network is investigated. The development time and cost for implementing a high speed signal processing system can be considerably reduced because algorithm are implemented in software using commercially available digital signal processors. This method is based on a parallel block processing approach, where a continuously supplied input data is divided into blocks, and the blocks are processed concurrently by being assigned to each processor in the system. This approach not only requires a simple interconnection network but also reduces the number of communications among the processors very much. The data dependency of the blocks to be processed concurrently brings on dependency problems between the processors in the system. A systematic scheduling method has been developed by using a processors which can be used efficiently, the methods for solving dependency problems between the processors are investigated. Implementation procedures and results for FIR, recursive (IIR), and adaptive filtering algorithms are illustrated.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.188-198
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• 1994

The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.

• The Journal of the Korea Contents Association
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• v.16 no.10
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• pp.608-616
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• 2016

The Smith-Watrman (SW) algorithm is a local alignment algorithm which is one of important operations in DNA sequence analysis. The SW algorithm finds the optimal local alignment with respect to the scoring system being used, but it has a problem to demand long execution time. To solve the problem of SW, some methods to perform SW in distributed and parallel manner have been proposed. The ADAM which is a distributed and parallel processing framework for DNA sequence has parallel SW. However, the parallel SW of the ADAM does not consider that the SW is a dynamic programming method, so the parallel SW of the ADAM has the limit of its performance. In this paper, we propose a method to enhance the parallel SW of ADAM. The proposed parallel SW (PSW) is performed in two phases. In the first phase, the PSW splits a DNA sequence into the number of partitions and assigns them to multiple nodes. Then, the original Smith-Waterman algorithm is performed in parallel at each node. In the second phase, the PSW estimates the portion of data sequence that should be recalculated, and the recalculation is performed on the portions in parallel at each node. In the experiment, we compare the proposed PSW to the parallel SW of the ADAM to show the superiority of the PSW.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.1
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• pp.11-19
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• 2024

The increased utilization of the FFT in signal processing, cryptography, and various other fields has highlighted the importance of optimization. In this paper, we propose the implementation of an accelerator that processes the radix-2 16 points FFT algorithm more rapidly and efficiently than FFT implementation of existing studies, using FPGA(Field Programmable Gate Array) hardware. Leveraging the hardware advantages of FPGA, such as parallel processing and pipelining, we design and implement the FFT logic in the PL (Programmable Logic) part using the Verilog language. We implement the FFT using only the Zynq processor in the PS (Processing System) part, and compare the computation times of the implementation in the PL and PS part. Additionally, we demonstrate the efficiency of our implementation in terms of computation time and resource usage, in comparison with related works.