• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.429-440
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• 2008

As embedded system becomes more complex, software development becomes more important in the entire design process. Most embedded applications consist of multi -tasks, that are executed in parallel. So, dataflow model that expresses concurrency naturally is preferred than sequential programming language to develop multitask software. For the execution of multitasking codes, operating system is essential to schedule multi-tasks and to deal with the communication between tasks. But, it is needed to execute multitasking code without as when the target hardware platform cannot execute as or target platforms are candidates of design space exploration, because it is very costly to port as for all candidate platforms of DSE. For this reason, we propose the serialized multitasking code generation technique from dataflow specification. In the proposed technique, a task is specified with dataflow model, and generated as a C code. Code generation consists of two steps: First, a block in a task is generated as a separate function. Second, generated functions are scheduled by a multitasking scheduler that is also generated automatically. To make it easy to write customized scheduler manually, the data structure and information of each task are defined. With the preliminary experiment of DivX player, it is confirmed that the generated code from the proposed framework is efficiently and correctly executed on the target system.

• Journal of Distribution Science
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• v.9 no.2
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• pp.13-24
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• 2011

With the increasing market share of retailer brands, many authors have paid considerable attention to retailer brands. Before market liberalisation in 1996 in Korea, retailer brand market was led by the supermarket retailing format, although the first retailer brand product was developed by the department store format. In parallel with the entry of foreign multiple retailers, the retailer brand market has experienced rapid growth. Particularly, the expansion of Tesco UK with well-established retailing know-how into Korea has encouraged Tesco Korea to actively get involved in retailer brand program. As a result, Tesco Korea has led retailer brand market in the Korean marketplace. The research starts with the question of why Tesco Korea has achieved such a higher retailer brand share. Accordingly, this study is to explore how Tesco UK has transferred its own retailing knowledge into Tesco Korea, in terms of retailer brand program development. In order to explore why the retailer brand share of Tesco Korea is higher than that of its counterparts, the author adopted in-depth interview with prepared-questions and store observation as a research methodology. To examine working process as well as information flows within Tesco Korea and from UK to Korea, in-depth interview method is one of the most suitable research methodologies, because of the difficulty of quantifying information or data related to work flows. In addition, to increase the validity of information, the researcher had interviews with Tesco Korea supplier and store personnel. Based on these research techniques, this research explored how Tesco UK has influenced or advised Tesco Korea, particularly, from the point of view of knowledge transfer. Since the entry of Tesco UK into Korea as a joint-venture, the retailer brand market share of Tesco Korea has continuously increased. It would be expected that Tesco UK has helped Tesco Korea to settle down in the Korean market. During interviews with Tesco and a Tesco supplier, the researcher found that Tesco Korea has obviously taken an advantage of retailing know-how created by Tesco UK. Furthermore, the retailer brand development and handling process of Tesco Korea has been operated with the help of Tesco UK. This might mean that Tesco UK has directly or indirectly an impact on the improvement of Korean retailer brand development skills. As a mechanism to transfer retailing knowledge developed in the home market into the host market, one of the international retailers, Tesco UK has adopted many different ways such as annual meeting, trading meeting to import or export own retailer brand products, offering of operation manual developed by Tesco UK and buyer cooperation between Tesco UK and Korea, in order to share information. Through these communication techniques, the knowledge of Tesco UK has been transferred to Tesco Korea. This research accordingly suggests that retailer brand market share is apparently related to how sophisticated or advanced the knowledge of the retailer brand development and handling process of retailers are. It is also demonstrated by this research that advanced development and handling skills make a considerable contribution to increasing retailer brand share in markets with a lower share or no presence of retailer brands.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.217-230
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• 2012

This paper propose interacting test programming methods between test equipment and hardware unit to verify function and performance of the hardware unit under test. Proposed test program can minimizes the risk of failures when the unit is mounted on the aircraft by testing and verifying the unit under the worst stress condition. Also, Object oriented design using UML make it easy to apply in other equipments. Test program consists of architecture package and hardware package. Architecture package is in a role for system management, log analysis, message receiving and message analysis. Messages that are used by system management define messages for testing and defined messages is sent and received to test equipment through Ethernet. Hardware package is in a role for hardware management that is needed to be tested and is related to a system. Hardware to be tested is divided into internal test and transmission test. Internal test inspects hardware itself and reports the test results to the test equipment. Transmission test inspects communication device by sending or receiving data. All kinds of test is done in the worst condition of the test unit executing in parallel. Each device is tested at least 482 times and at most 15,003 times about one hour. Test program is utilized in hardware reliability test like as environmental test or EMI test.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.120-134
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• 2000

In this paper we present a Distributed Object oriented Virtual computing Environment, called DOVE which consists of autonomous distributed objects interacting with one another via method invocations based on a distributed object model. DOVE appears to a user logically as a single virtual computer for a set of heterogeneous hosts connected by a network as if objects in remote site reside in one virtual computer. By supporting efficient parallelism, heterogeneity, group communication, single global name service and fault-tolerance, it provides a transparent and easy-to-use programming environment for parallel applications. Efficient parallelism is supported by diverse remote method invocation, multiple method invocation for object group, multi-threaded architecture and synchronization schemes. Heterogeneity is achieved by automatic data arshalling and unmarshalling, and an easy-to-use and transparent programming environment is provided by stub and skeleton objects generated by DOVE IDL compiler, object life control and naming service of object manager. Autonomy of distributed objects, multi-layered architecture and decentralized approaches in hierarchical naming service and object management make DOVE more extensible and scalable. Also,fault tolerance is provided by fault detection in object using a timeout mechanism, and fault notification using asynchronous exception handling methods

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.55 no.4
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• pp.294-302
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• 2019

As a series of fundamental researches on the development of an automatic identification monitoring system for fishing gear. Firstly, the study on the installation method of automated identification buoy for the coastal improvement net fishing net with many loss problems on the west coast was carried out. Secondly, the study was conducted find out how to install an automatic identification buoy for coastal gill net which has the highest loss rate among the fisheries. GPS for fishing was used six times in the coastal waters around Seogwipo city in Jeju Island to determine the developmental status and underwater behavior to conduct a field survey. Next, a questionnaire was administered in parallel on the type of loss and the quantity and location of fishing gear to be developed and the water transmitter. In the field experiment, the data collection was possible from a minimum of 13 hours, ten minutes to a maximum of 20 hours and ten minutes using GPS, identifying the development status and underwater behavior of the coastal gillnet fishing gear. The result of the survey showed that the loss of coastal net fishing gear was in the following order: net (27.3%), full fishing gear (24.2%), buoys, and anchors (18.2%). The causes were active algae (50.0%), fish catches (33.3%) and natural disasters (12.5%). To solve this problem, the installation method is to attach one and two electronic buoys to top of each end of the fishing gear, and one underwater transmitter at both ends of the float line connected to the anchor. By identifying and managing abnormal conditions such as damage or loss of fishing gear due to external factors such as potent algae and cutting of fishing gear, loss of fishing gear can be reduced. If the lost fishing gear is found, it will be efficiently collected.

• The Journal of the Korea Contents Association
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• v.17 no.1
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• pp.12-24
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• 2017

The purpose of this study was to evaluate the effects of personality virtue education program using visual media for college students. This program was run in parallel with "Educational Psychology" lecture from August 30th through December 4th, 2015. The subjects of study were 348 freshmen of nursing department in J college. The methodology of this study was nonequivalent pretest-posttest control group experimental design. The researcher carried out pretest for experimental group and control group both before program execution by KEDI Personality Inventory and repeated the test afterwards to measure the effects of the program. The data analysis was implemented by SPSS 22.0. The ANCOVA was used to verify the hypothesis. The result showed that all personality virtues(self-respect, integrity, consideration communication, responsibility, etiquette, self-control, honesty courage, wisdom, justice, citizenship) scores were improved significantly after the program. In conclusion, virtue-centered personality education can make students realize and internalize the value of virtues and have motivation and will to act, when they empathized with visual media on the various situation and learned repeatedly in integrated curriculum.

• Science of Emotion and Sensibility
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• v.8 no.3
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• pp.221-229
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• 2005

This study aimed to understand the sex differences in cognitive behaviors in website design and demonstrate a practical basis for utilizing these differences into more user-centered design concept. Especially, we focused on the sex-different preference according to the information architecture of website navigation. First, We investigated general differences between men and women in cognitive behaviors through various literature studies. According to our investigation, men's cognitive works generally tend to follow a regular sequence and proceed step by step. On the other hand, women's cognitive style is generally characterized by random generation and simultaneous progress. To examine that these differences can be found in use of website navigation, we made an experiment in website design. We designed several test websites that have same contents but different style of navigation structure. A similar number of men and women were chosen for this test and they implemented given tasks. During the test, participants reported their preference on each websites and their implementing time and number of errors were collected. Based on the analysis of test data, it was possible to conclude that male participants' preference for the navigation with a narrow and deep information structure is relatively higher than female participants' preference for the same navigation, On the other hand, female participants have a preference of the navigation with a broad and swallow information structure. The result of study showed that there is a close correlation between the sex differences in preference of navigation types and the general sex differences in cognitive behavior. This finding can be used as a basis for designing the website navigation in which sex differences are reflected.