• 전기의세계
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• v.28 no.9
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• pp.35-40
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• 1979

A grounded inductor is proposed which contains only one resistor and operational amplifier. The circuit uses the inherent frequency dependent characteristic of an amplifier to simulate the inductor. A parallel resonance circuit is constructed with the proposed circuit. It has been proved by the experimental results of the resonant circuit that the proposed circuit is equivalent to the grounded lossy inductor. The lossy inductor is imbedded in a passive bandstop prototype, and the resultant characteristic curve has been verified by the experiment.

• Journal of electromagnetic engineering and science
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• v.11 no.3
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• pp.166-173
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• 2011

In this paper, we implemented and analyzed a wireless power transfer (WPT) system with a CSPR topology. CSPR refers to constant current source, series resonance circuit topology of a transmitting coil, parallel resonance circuit topology of a receiving coil, and pure resistive loading. The transmitting coil is coupled by a magnetic field to the receiving coil without wire. Although the electromotive force (emf) is small (about 4.5V), the voltage on load resistor is 148V, because a parallel resonance scheme was adopted for the receiving coil. The implemented WPT system is designed to be able to transfer up to 1 kW power and can operate a LED TV. Before the implementation, the EMF reduction mechanism based on the use of ferrite and a metal shield box was confirmed by an EM simulation and we found that the EMF can be suppressed dramatically by using this shield. The operating frequency of the implemented WPT system is 30.7kHz and the air gap between two coils is 150mm. The power transferred to the load resistor is 147W and the real power transfer efficiency is 66.4 %.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.128-137
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• 2015

A novel parallel three-level zero voltage switching (ZVS) DC converter is presented for medium voltage applications. The proposed converter includes three sub-circuits connected in parallel with the same power switches to share load current and reduce the current stress of passive components at the output side. Thus, the size of the output chokes is reduced and the switch counts in the proposed converter are less that in the conventional parallel three-level DC/DC converter. Each sub-circuit combines one half-bridge converter and one three-level converter. The transformer secondary windings of these two converters are connected in series in order to reduce the size of output inductor. Due to the three-level circuit topology, the voltage stress of power switches is equal to $V_{in}/2$. Based on the resonant behavior by the output capacitance of power switches and the leakage inductance (or external inductance) at the transition interval, each switch can be turned on under ZVS. Finally, experiments based on a 2 kW prototype are provided to verify the performance of the proposed converter.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.412-415
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• 2008

In a research on the practical dye-sensitized solar cell, a study on a large module have preference because module must be able to generate the proper current that is possible to convert electrically. So the parallel connection of dye-sensitized solar cells which outputs a large current easily is essential. However, there is a current loss in a paralle connection of dye-sensitized solar cells and the loss becomes larger according to increasing the number of parallel connection. In this study, we analyzed the cause of the current loss in the parallel connection by using the equivalent circuit analysis. One DSC used in this experiment had an active area $8cm^2$(4.62cm$\times$1.73cm) and it attained a conversion efficiency of 5.43% under 1 sun illumination ($P_{in}$ of 100 mW/$cm^2$) using a solar simulator.

• Journal of KIISE:Software and Applications
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• v.37 no.8
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• pp.647-652
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• 2010

Esterel is an imperative synchronous language well-adapted to control-intensive systems. When an Esterel program is translated to a circuit, the synchronizer of a parallel statement may be executed more than once in a clock; the synchronizer is called schizophrenic. Existing compilers cure the problems of schizophrenic parallel synchronizers using logic duplications. This paper proposes the conditions under which a synchronizer causes no problem in circuits when it is executed more than once in a clock. In addition we design a detection algorithm based on those conditions. Our algorithm detects schizophrenic parallel synchronizers that have to be duplicated in Esterel source codes so that compilers can save the size of synthesized circuits

• Journal of Korean Society of Industrial and Systems Engineering
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• v.29 no.2
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• pp.7-12
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• 2006

This study considers the problem of scheduling jobs on uniform parallel machines with a common due date. The objective is to minimize the total absolute deviation of job completion times about the common due date. This problem is motivated by the fact that a certain phase of printed circuit board manufacturing is bottleneck and the processing speeds of parallel machines in this phase are uniformly different for all jobs. Optimal properties are proved and a simple polynomial time optimal algorithm is developed.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.36-43
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• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• Progress in Superconductivity and Cryogenics
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• v.14 no.3
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• pp.13-17
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• 2012

KEPCO Research Institute has been researching a Superconducting Fault Current Limiter (SFCL) which is considered one of solutions of fault current problems with Korea Institute of Machinery & Materials (KIMM) and Hanyang University since 2011. In this paper, we fabricated a current limiting module and conducted electrical short circuit tests for checking the validity of the transmission level SFCL design. Based on the short circuit characteristics of the second generation High Temperature Superconductor (HTS), we analyzed the short circuit characteristics of 3 parallel connected superconducting wires. The structure of the HTS wire is as follows: the stainless steel stabilizer of $100{\mu}m$ is laminated on the superconductor layer and under the substrate, both of which are electrically jointed with solder. We fabricated the current limiting module which has 40 series and 6 parallel connections and studied the short circuit characteristics of the module under various voltage levels.

• Proceedings of the SAREK Conference
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• 2007.11a
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• pp.216-221
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• 2007

An experiment was carried out to investigate the effect of a coolant circuit arrangement on the heat transfer and air pressure drop of a fin-tube sensible heat exchanger with the corrugated fin surface. The air inlet temperature was set to $23^{\circ}C$,the relative humidity to 50% and the air inlet flow rate to 20, 22, $25m^3/min$, respectively. while the coolant temperature was set to $7^{\circ}C$, and the coolant mass flow rate to 10, 16, 22kg/min, respectively. Experiment showed that the exchanger having a diameter of 12.7mm with parallel circuit does better performance in sensible heat transfer and air pressure drop than those three of diameter of 12.7mm with a series circuit and that with diameter of 15.88mm with a parallel circuit.