Reducing False Alarms in Schizophrenic Parallel Synchronizer Detection for Esterel

Esterel에서 동기장치 중복사용 문제 검출시 과잉 경보 줄이기

  • Received : 2010.04.13
  • Accepted : 2010.06.10
  • Published : 2010.08.15

Abstract

Esterel is an imperative synchronous language well-adapted to control-intensive systems. When an Esterel program is translated to a circuit, the synchronizer of a parallel statement may be executed more than once in a clock; the synchronizer is called schizophrenic. Existing compilers cure the problems of schizophrenic parallel synchronizers using logic duplications. This paper proposes the conditions under which a synchronizer causes no problem in circuits when it is executed more than once in a clock. In addition we design a detection algorithm based on those conditions. Our algorithm detects schizophrenic parallel synchronizers that have to be duplicated in Esterel source codes so that compilers can save the size of synthesized circuits

Esterel이라는 절차형(imperative) 동기(synchronous) 언어로부터 회로를 합성(synthesis)할 때, 하나의 동기장치(synchronizer)가 한 클럭에 중복사용되는 문제(schizophrenic parallel synchronizer)가 발생할 수 있다. 기존 컴파일러는 동기장치가 중복사용될 경우 동기장치를 복제하여 이 문제를 해결하고 있다. 본 논문은 동기장치가 중복사용되더라도 회로상/기능상 문제가 없는 조건을 제시하고, 이를 기반으로 소스코드를 분석하여 복제해야만 하는 동기장치를 찾아주는 알고리즘을 제안한다. 이 알고리즘은 컴파일러가 중복사용되는 동기장치들 중에서 꼭 복제해야만 하는 것을 알 수 있게 해 주어, Esterel 프로그램을 좀 더 작은 회로로 합성할 수 있도록 한다.

Keywords

References

  1. N. Halbwachs, Synchronous Programming of Reactive Systems, Kluwer Academic Publishers, 1993.
  2. A. Benveniste, P. Caspi, S. A. Edwards, N. Halbwachs, P. Le Guernic, and R. de Simone, "The synchronous languages 12 years later," Proceedings of the IEEE Embedded Systems, vol.91(1), pp.64-83, 2003.
  3. G. Berry. The Constructive Semantics of Pure Esterel. Draft book available at http://www.inria.fr/meije/esterel/esterel-eng.html, 1999.
  4. D. Potop-Butucaru, S. A. Edwards, and G. Berry. Compiling Esterel. Springer, 2007.
  5. Esterel Technologies. The Esterel v7 Reference Manual Version v7.30. initial IEEE standardization proposal. Esterel Technologies, 679 av. Dr. J. Lefebvre 06270 VilleneuveLoubet, France, November, 2005.
  6. O. Tardieu and R. de Simone, "Loops in Esterel," Transactions on Embedded Computing Systems, vol.4, no.4, pp.708-750, 2005. https://doi.org/10.1145/1113830.1113832
  7. K. Schneider, J. Brandt, and T. Schuele, "A verified compiler for synchronous programs with local declarations," Electronic Notes in Theoretical Computer Science, vol.153, no.4, pp.71-97, 2006. https://doi.org/10.1016/j.entcs.2006.02.028
  8. G. Berry, "Circuit design and verification with Esterel v7 and Esterel Studio," IEEE International High-Level Design, Validation, and Test Workshop, pp.133-136, 2007.
  9. M. Yoeli and S. Rinon, "Application of ternary algebra to the study of static hazards," Journal of ACM, vol.11, no.1, pp.84-97, 1964. https://doi.org/10.1145/321203.321214
  10. S. Malik, "Analysis of cyclic combinational circuitsM" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.13, no.7(7), pp.950-956, 1994. https://doi.org/10.1109/43.293952
  11. M. D. Riedel and J. Bruck, "Cyclic boolean circuits," Journal of Discrete Applied Mathematics, 2009.
  12. C. Kim, J. Yun, S. Seo, K. Choe, and T. Han, "Over-approximated Control Flow Graph Construction on Pure Esterel," IEICE Transactions on Information and Systems, vol.E93-D, no.5, May 2010 (accepted).
  13. J. Yun, C. Kim, S. Seo, T. Han, and K. Choe, "Refining schizophrenia via graph reachability in Esterel," 7th ACM-IEEE International Conference on Formal Methods and Models for Codesign, 2009.
  14. S. Ramesh, Ramesh's homepage. http://www.cse.iitb.ac.in/-ramesh