• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.2 no.4
• /
• pp.553-558
• /
• 1998

We present in this paper the ture union bound of the performance of chip level detection for coded DS/CDMA system operating in Rician fading channels such as LEO satellite mobile radio where the maximum doppler frequency is very high. The main objective of this paper is to calculate the exact doe union bound of BER performance of different performance of different quadrature detectors and to find a optimum spreading factor as a function of fade rate. The rationale of using multiple chip detection is to reduce the effective fade rate or variation. We considered chip level differential detection, chip level maximum likelihood sequence estimation, noncoherent detection and coherent detection with perfect channel state information as a reference.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.1187-1188
• /
• 2008

An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
• /
• 2004.10a
• /
• pp.463-467
• /
• 2004

This paper presents the fabrication possibility of the micro actuator which uses a micro-thermal bubble, generated b micro-heater under pulse heating. The valve-less micropump using the diffuser/nozzle is consists of the lower plate, he middle plate, the upper plate. The lower plate includes the channel and chamber are fabricated on high processability silicon wafer by the DRIE(Deep Reactive Ion Etching) process. The middle plate includes the chamber and diaphragm d the upper plate is the micro-heater. The Micropump is fabricated by bonding process of the three layer. This paper resented the possibility of the PCR chip operation by the fabricated micropump.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.15 no.1
• /
• pp.139-144
• /
• 1991

Chip flow angle is one of the important factors to be determined for the scheme of Chip Control. Up to now, however, a dependable way to predict the chip flow angle in practical cutting has not been established satisfactorily. In this paper a rather simple theoretical prediction of chip flow angle is tried based on some already widely confirmed hypotheses. The developed equation of chip flow angle contains the parameters of depth of cut d, feed rate f, nose radius $r_{n}$ side cutting edge angle $C_{s}$, side rake angle .alpha.$_{s}$ and back rake angle .alpha.$_{b}$. Theoretical results of chip flow angle given by this study bas been shown in a good agreement with experimental ones.s.s.s.s.

• Journal of the Korean Society for Precision Engineering
• /
• v.20 no.11
• /
• pp.64-70
• /
• 2003

This paper suggests a systematic methodology to predict chip forms using the experimental design technique and the neural network. Significant factors determined with ANOVA analysis are used as input variables of the neural network back-propagation algorithm. It has been shown that cutting conditions and cutting tool shapes have distinct effects on the chip forms, so chip breaking. Cutting tools are represented using the Z-map method, which differs from existing methods using some chip breaker parameters. After training the neural network with selected input variables, chip forms are predicted and compared with original chip forms obtained from experiments under same input conditions, showing that chip forms are same at all conditions. To verify the suggested model, one tool not used in training the model is chosen and input to the model. Under various cutting conditions, predicted chip forms agree well with those obtained from cutting experiments. The suggested method could reduce the cost and time significantly in designing cutting tools as well as replacing the“trial-and-error”design method.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.20 no.5
• /
• pp.559-563
• /
• 2011

Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

• Journal of the Korea Society for Simulation
• /
• v.26 no.1
• /
• pp.69-75
• /
• 2017

An MCP(Multi-chip Package) is a package consisting of several chips. Since several chips are stacked on the same substrate, multiple assembly steps are required to make an MCP. The characteristics of the chips in the MCP are dependent on the layer sequence. In the MCP manufacturing process, it is very essential to carefully consider the layer sequence in scheduling to achieve the intended throughput as well as the WIP balance. In this paper, we propose a scheduling methodology considering the layer sequence constraint.

• Journal of the Microelectronics and Packaging Society
• /
• v.6 no.4
• /
• pp.61-71
• /
• 1999

The recent trend toward higher frequencies, miniaturization and lower-cost in wireless communication equipment is demanding high density packaging technologies such flip chip interconnection and multichip module(MCM) as a substitute of conventional plastic package. With analyzing the recently reported research results of the RF flip chip, this paper presents the technical issues and advantages of RF flip chip and suggest the flip chip technologies suitable for the development stage. At first, most of RF flip chips are designed in a coplanar waveguide line instead of microstrip in order to achieve better electrical performance and to avoid the interaction with a substrate. Secondly, eliminating wafer back-side grinding, via formation, and back-side metallization enables the manufacturing cost to be reduced. Finally, the electrical performance of flip chip bonding is much better than that of plastic package and the flip chip interconnection is more suitable for Transmit/Receiver modules at higher frequency. However, the characterization of CPW designed RF flip chip must be thoroughly studied and the Au stud bump bonding shall be suggested at the earlier stage of RF flip chip development.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.567-570
• /
• 1988

This paper describes the design of FIR filtering DSP-chip that can be operated without programming. The proposed DSP-chip has not only the improvement of execution time but also selectivity of filter length from N=1 to N=128. Hilbert Transformer can be designed from this chip. FIR filter system is composed of Data memory/Control Unit, external memory and multiplier-accumulator. Data memory/Control Unit is laid out in this paper.

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.15 no.2
• /
• pp.73-80
• /
• 2006

This paper describes a analysis on the chip thickness model required for cutting force simulation in ball-end milling. In milling, cutting forces are obtained by multiplying chip area to specific cutting forces in each cutting instance. Specific cutting forces are one of the important factors for cutting force predication and have unique value according to workpiece materials. Chip area in two dimensional cutting is simply calculated using depth of cut and feed, but not simply obtained in three dimensional cutting such as milling due to complex cutting mechanics. In ball-end milling, machining is almost performed in the ball part of the cutter and tool radius is varied along contact point of the cutter and workpiece. In result, the cutting speed and the effective helix angle are changed according to length from the tool tip. In this study, for chip thickness model analysis, tool and chip geometry are analyzed and then the definition of chip thickness and estimation method are described. The resulted of analysis are verified by compared with geometrical simulation and other research. The proposed chip thickness model is more precise.