• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.117-120
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• 2001

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.361-364
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• 2001

This paper presents a simple method for estimating the maximum crosstalk noise of on-chip grobal wires. For the derivation of the maximum crosstalk expression we have modeled wires using lumped-elements that are composed of R, L and C. We have also used experimental constant to reduce the modeling error. The accuracy of the proposed method is verified by comparing against the HSPICE simulation results under the present process parameters and environmental conditions. The results of the proposed method can be used as an estimator in design-aid tools.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.222-224
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• 2000

This Paper investigates the speed control of Switched reluctance motor(SRM) using one chip microcomputer The SRM has the advantages of simple structure low rotor inertia. and high efficiency. The Position sensor is essential in SRM in order to synchronize the Phase excitation to the rotor position. The proposed system consists of phase locked loop controller, switching angle controller and inverter. The Performances in the Proposed system are verified through the experiment.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2212-2215
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• 2003

In this paper, we proposed speech feature vector extractor for embedded system using TMS 320C31 DSP chip. For this extractor, we used algorithm using cepstrum coefficient based on LPC(Linear Predictive Coding) that is reliable algorithm to be is widely used for speech recognition. This system extract the speech feature vector in real time, so is used the mobile system, such as cellular phones, PDA, electronic note, and so on, implemented speech recognition.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2240-2243
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• 2003

In this paper. we present a new speech recognition system using DSP chip. DSP chip used TMS320c6711 of TI. We designed hardware system including acoustic model, word list and code book in flash memory. The word candidates are recognized based on CV, VCCV, and VC units HMM. This system can be applied to various electric ＆ electronic devices: home automation, robotics etc.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.4
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• pp.1-8
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• 1977

Microprocessor which is opened to the user, not fixed in CPU chip, has been appeared. In this Paper, Microprogram and Mapping Array designed to make functions of NOVA-01 emulate to $\mu$COM-16.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.389-393
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• 2003

This paper presents circuit modeling and characterization of silicon-based on-chip integrated inductors in Giga Hertz range for wireless communication products. We compare several different designs of on-chip inductors for self-resonant frequency and quality factor. The measurement data could be used as a design guide for manufacturing practical spiral inductors for wireless applications. We provide the equivalent inductor circuit parameters from the actual measurement data.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.963-968
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• 2002

This paper will review the driving methods and issues of driving circuitry for passive matrix organic electro-luminescent displays(PM-OELDs). And it will shows the proposed one-chip and two-chip solution for driving the PM-OELDs and also the pixel structure and driving methods of active matrix (AM-OELDs). We will discuss the proper applications of OELDs with its power consumption by comparison with that of LCD.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.345-348
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• 2001

The paper describes the physical design flow & verification of Digital Video Broadcasting(DVB) compliant satellite receiver chip. It includes problems and issues of earth design flow, verification process for physical layout.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.588-592
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• 1996

In this paper, we have constructed an expert system for semiconductor chip encapsulation which combines a knowledge-based system with CAE software. The knowledge-base module includes heuristic and pre-analysis knowledge for evaluation and redesign. Evaluation of the initial design and generation of redesign recommendations can be developed from the rules as applied to a given chip Package. The CAE programs can be used for simulating the filling and packing stage of encapsulation process. The expert system is a new tool which enables package design or process conditions with high yields and high productivity.