• 대한설비공학회:학술대회논문집
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• 대한설비공학회 2009년도 하계학술발표대회 논문집
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• pp.780-785
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• 2009

The photovoltaic/thermal collectors (PV/T collectors) combine the solar thermal collector and photovoltaic modules. They can produce thermal energy in the form of hot air or hot water, and converts solar radiation into electricity. The collecctors can improve the electrical performance of PV modules as the heat from the PV module carried away by the thermal part of the system keeping temperatures lower. The basic water cooled PVT collector has metallic water pipes attached to the back of a PV collector. There are main parameters affecting the performance (electrical and thermal) of PVT collectors. This paper analyzed the experimental performance of glazed water PVT module, considering the parameters of solar radiation, inlet water temperature and ambient temperature. It found that solar radiation is the dominant factor for the electrical performance of the collector, and for the thermal performance the inlet water temperature and ambient temperature appeared to be more related.

• 전기전자학회논문지
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• 제27권3호
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• pp.234-238
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• 2023

본 논문에서는 PVT(process, voltage, and temperature) 변화에 대한 보상기능을 가지는 시간-디지털 변환기(time-to-digital converter : TDC)를 제안한다. 일반적인 지연 라인(delay line) 기반의 TDC는 인버터의 전파 지연을 기반으로 시간을 측정하기 때문에 근본적으로 PVT 변화에 민감하다. 이 논문은 PVT 변화에 의한 전파 지연을 보상하여 TDC의 해상도 변화를 최소화시키는 방법을 제안한다. 또한 넓은 입력 측정 범위(detection range)를 갖기 위해 Cyclic Vernier TDC (CVTDC) 구조를 채택한다. 제안하는 PVT보상 기능의 CVTDC는 45nm CMOS 공정으로 설계되어, 8mW의 전력을 소모하며, 5 ps의 TDC 해상도 및 약 5.1 ns 입력 측정 범위를 갖는다.

• Journal of Information Processing Systems
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• 제7권1호
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• pp.93-102
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• 2011

In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency "dynamically". The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated "automatically". During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS'85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.375-378
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• 2013

본 논문에서는 EEPROM이나 MTP 등의 NVM 메모리 IP 설계에 필요로 하는 PVT(Process-Voltage-Temperature) 변동에 둔감한 기준전압(Reference Voltage) 회로를 설계하였다. 매그나칩반도체 $0.18{\mu}m$ EEPROM 공정을 이용하여 설계된 BGR(Bandgap Reference Voltage) 회로는 wide swing을 갖는 캐스코드 전류거울 (cascode current-mirror) 형태의 저전압 밴드갭 기준전압발생기 회로를 사용하였으며, PVT 변동에 둔감한 기준전압 특성을 보이고 있다. 최소 동작 전압은 1.43V이고 VDD 변동에 대한 VREF 민감도(sensitivity)는 0.064mV/V이다. 그리고 온도 변동에 대한 VREF 민감도는 $20.5ppm/^{\circ}C$이다. 측정된 VREF 전압은 평균 전압이 1.181V이고 $3{\sigma}$는 71.7mV이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.593-594
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• 2008

In this article, process voltage temperature (PVT) compensated on-chip oscillator is implemented by using proportional to absolute temperature (PTAT) circuit and process compensator. Process compensator circuit based on current subtracter and PTAT circuit are proposed for compensation of oscillation frequency to cope with process variation and temperature variation. All circuit can operate in the range of $3.5{\sim}5\;V$ supply voltage. It can be applied to PVT insensitive low frequency clock reference generator.

• 한국결정성장학회지
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• 제30권5호
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• pp.163-167
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• 2020

본 연구에서는 PVT(Physical Vapor Transport) 방법을 이용하여 반도체 식각 공정용 소재로 사용되는 링 모양의 SiC(Silicon carbide) 다결정을 제조하였다. 흑연 도가니 내부에 원기둥 모양의 흑연 구조물을 배치하여 PVT법에 의한 링 모양의 SiC 다결정을 성장시켰다. 성장된 결정은 Raman 및 UVF(Ultra Violet Fluorescence) 분석을 이용하여 결정의 상분석을 하였고, SEM(Scanning Electron Microscope), EDS(Energy Dispersive Spectroscopy) 분석을 통해 미세조직 및 성분을 확인하였다. PVT 성장 초기의 온도변화를 통하여 SiC 다결정의 결정립 크기와 성장 속도를 조절할 수 있었다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 추계종합학술대회
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• pp.785-788
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• 2007

새롭게 제안된 밴드갭 기준전압 발생기는 PVT변동에 둔감하면서 기존의 밴드갭 기준전압 발생기보다 안정적인 동작을 하기 위해 요구되는 최소 전원전압(VDD)의 크기을 낮추었다. 모의실험 결과 전원전압(VDD)이 1.0V의 낮은 전압에서 안정적인 동작을 하는 것을 확인 하였다. 매그나칩 반도체 $0.18{\mu}m$ DDI 공정을 이용하여 Layout 하였고, 사이즈는 $409.36{\mu}m$ ${\times}$ $435.46{\mu}m$ 이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.333-336
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• 2000

Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.

• Korea-Australia Rheology Journal
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• 제16권4호
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• pp.163-168
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• 2004

In this study, an ultrasonic technique was employed to obtain pressure-volume-temperature (PVT) rela­tionship of polymer melt by measuring ultrasonic velocities under various temperatures and pressures. The proposed technique was applied to on-line monitoring of injection molding process as an attempt to predict quality of molded parts. From the comparison based on Tait equation, it was confirmed that the PVT behav­ior of a polymer is well described by the variation of ultrasonic velocities measured within the polymer medium. In addition, the changes in part weight and moduli were successfully predicted by combining the data collected from ultrasonic technique and artificial neural network algorithm. The results found from this study suggest that the proposed technique can be effectively utilized to monitor the evolution of solid­ification within the mold by measuring ultrasonic responses of various polymers during injection molding process. Such data are expected to provide a critical basis for the accurate prediction of final performance of molded parts.

• 소성∙가공
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• 제13권2호
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• pp.180-187
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• 2004

A computer code was developed to simulate the filling stage of the injection/compression molding process by a finite element method. The constitutive equation used here was the compressible Leonov model. The PVT relationship was assumed to follow the Tait equation. The flow-induced birefringence was related to the calculated flow stresses through the linear stress-optical law. Simulations of a disk part under different process conditions including the variation of compression stroke and compression speed were carried out to understand their effects on birefringence variation. The simulated results were also compared with those by conventional injection molding.