• Title/Summary/Keyword: PVT variation

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An Experimental Study of PV/Thermal Combined Collector Module (평판형 액체식 PVT 모듈의 성능 실험 분석)

  • Kang, Jun-Gu;Kim, Jin-Hee;Kim, Jun-Tae
    • Proceedings of the SAREK Conference
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    • 2009.06a
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    • pp.780-785
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    • 2009
  • The photovoltaic/thermal collectors (PV/T collectors) combine the solar thermal collector and photovoltaic modules. They can produce thermal energy in the form of hot air or hot water, and converts solar radiation into electricity. The collecctors can improve the electrical performance of PV modules as the heat from the PV module carried away by the thermal part of the system keeping temperatures lower. The basic water cooled PVT collector has metallic water pipes attached to the back of a PV collector. There are main parameters affecting the performance (electrical and thermal) of PVT collectors. This paper analyzed the experimental performance of glazed water PVT module, considering the parameters of solar radiation, inlet water temperature and ambient temperature. It found that solar radiation is the dominant factor for the electrical performance of the collector, and for the thermal performance the inlet water temperature and ambient temperature appeared to be more related.

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A Time-to-Digital Converter with PVT Variation Compensation Capability (PVT 변화 보상 기능을 가지는 시간-디지털 변환기)

  • Eunho Shin;Jongsun Kim
    • Journal of IKEEE
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    • v.27 no.3
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    • pp.234-238
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    • 2023
  • In this paper, we propose a time-to-digital converter (TDC) with compensation capability for PVT (process, voltage, and temperature) variations. A typical delay line-based TDC measures time based on the inverter's propagation delay, making it fundamentally sensitive to PVT variations. This paper presents a method to minimize the resolution change of TDC by compensating for the propagation delay caused by the PVT variations. Additionally, it dopts Cyclic Vernier TDC (CVTDC) structure to provide a wide input detection range. The proposed CVTDC with PVT compensation function is designed using a 45nm CMOS process, consumes 8mW of power, offers a TDC resolution of 5 ps, and has an input detection range of about 5.1 ns.

Dynamic Voltage and Frequency Scaling for Power-Constrained Design using Process Voltage and Temperature Sensor Circuits

  • Nan, Haiqing;Kim, Kyung-Ki;Wang, Wei;Choi, Ken
    • Journal of Information Processing Systems
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    • v.7 no.1
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    • pp.93-102
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    • 2011
  • In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency "dynamically". The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated "automatically". During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS'85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.

Design of Low-Voltage Reference Voltage Generator for NVM IPs (NVM IP용 저전압 기준전압 회로 설계)

  • Kim, Meong-Seok;Jeong, Woo-Young;Park, Heon;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.375-378
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    • 2013
  • A reference voltage generator which is insensitive to PVT (process-voltage-temperature) variation necessary for NVM memory IPs such as EEPROM and MTP memories is designed in this paper. The designed BGR (bandgap reference voltage) circuit based on MagnaChip's $0.18{\mu}m$ EEPROM process uses a low-voltage bandgap reference voltage generator of cascode current-mirror type with a wide swing and shows a reference voltage characteristic insensitive to PVT variation. The minimum operating voltage is 1.43V and the VREF sensitivity against VDD variation is 0.064mV/V. Also, the VREF sensitivity against temperature variation is $20.5ppm/^{\circ}C$. The VREF voltage has a mean of 1.181V and its three sigma ($3{\sigma}$) value is 71.7mV.

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On-Chip CMOS Oscillator using PVT Compensated Circuit (공정, 전압, 온도 보상 회로를 이용한 On-Chip CMOS Oscillator)

  • Han, Do-Hee;Kwon, Ick-Jin
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.593-594
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    • 2008
  • In this article, process voltage temperature (PVT) compensated on-chip oscillator is implemented by using proportional to absolute temperature (PTAT) circuit and process compensator. Process compensator circuit based on current subtracter and PTAT circuit are proposed for compensation of oscillation frequency to cope with process variation and temperature variation. All circuit can operate in the range of $3.5{\sim}5\;V$ supply voltage. It can be applied to PVT insensitive low frequency clock reference generator.

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Crystal growth of ring-shaped SiC polycrystal via physical vapor transport method (PVT 방법에 의한 링 모양의 SiC 다결정 성장)

  • Park, Jin-Yong;Kim, Jeong-Hui;Kim, Woo-Yeon;Park, Mi-Seon;Jang, Yeon-Suk;Jung, Eun-Jin;Kang, Jin-Ki;Lee, Won-Jae
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.30 no.5
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    • pp.163-167
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    • 2020
  • Ring-shaped SiC (Silicon carbide) polycrystals used as an inner material in semiconductor etching equipment was manufactured using the PVT (Physical Vapor Transport) method. A graphite cylinder structure was placed inside the graphite crucible to grow a ring-shaped SiC polycrystal by the PVT method. The crystal polytype of grown crystal were analyzed using a Raman and an UVF (Ultra Violet Fluorescence) analysis. And the microstructure and components of SiC crystal were identified by a SEM (Scanning Electron Microscope) and EDS (Energy Disruptive Spectroscopy) analyses. The grain size and growth rate of SiC polycrystals fabricated by this method was varied with temperature variation in the initial stage of growth process.

A Low Voltage Bandgap Reference Voltage Generator Design and Measurement (저전압 밴드갭 기준 전압 발생기 설계)

  • Shim, Oe-Yong;Lee, Jae-Hyung;Kim, Jong-Hee;Kim, Tae-Hoon;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.10a
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    • pp.785-788
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    • 2007
  • The newly proposed badgap reference voltage generator is insensible to PVT(process, voltage, temperature) variation and has a lower minimum supply voltage, which is required for stable operation. The simulation result is that the bandgap reference voltage generator starts operation at 1.0V of supply voltage. The layout of the bandgap reference voltage generator is designed using Magnachip $0.18{\mu}m$ DDI process, and the size is $409.36{\mu}m$ ${\times}$ $435.46{\mu}m$.

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A Phase-Locked Loop Using Switched-Capacitor Loop Filter (Switched-Capacitor 루프 필터를 이용한 Phase-Locked Loop의 설계)

  • 최근일;이용석
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.333-336
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    • 2000
  • Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.

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Investigation of pressure-volume-temperature relationship by ultrasonic technique and its application for the quality prediction of injection molded parts

  • Kim Jung Gon;Kim Hyungsu;Kim Han Soo;Lee Jae Wook
    • Korea-Australia Rheology Journal
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    • v.16 no.4
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    • pp.163-168
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    • 2004
  • In this study, an ultrasonic technique was employed to obtain pressure-volume-temperature (PVT) rela­tionship of polymer melt by measuring ultrasonic velocities under various temperatures and pressures. The proposed technique was applied to on-line monitoring of injection molding process as an attempt to predict quality of molded parts. From the comparison based on Tait equation, it was confirmed that the PVT behav­ior of a polymer is well described by the variation of ultrasonic velocities measured within the polymer medium. In addition, the changes in part weight and moduli were successfully predicted by combining the data collected from ultrasonic technique and artificial neural network algorithm. The results found from this study suggest that the proposed technique can be effectively utilized to monitor the evolution of solid­ification within the mold by measuring ultrasonic responses of various polymers during injection molding process. Such data are expected to provide a critical basis for the accurate prediction of final performance of molded parts.

Finite Element Analysis of Injection/Compression Molding Process (사출압축성형 공정에 대한 유한요소 해석)

  • 이호상
    • Transactions of Materials Processing
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    • v.13 no.2
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    • pp.180-187
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    • 2004
  • A computer code was developed to simulate the filling stage of the injection/compression molding process by a finite element method. The constitutive equation used here was the compressible Leonov model. The PVT relationship was assumed to follow the Tait equation. The flow-induced birefringence was related to the calculated flow stresses through the linear stress-optical law. Simulations of a disk part under different process conditions including the variation of compression stroke and compression speed were carried out to understand their effects on birefringence variation. The simulated results were also compared with those by conventional injection molding.