• Title/Summary/Keyword: PVT insensitive

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Design of Low-Voltage Reference Voltage Generator for NVM IPs (NVM IP용 저전압 기준전압 회로 설계)

  • Kim, Meong-Seok;Jeong, Woo-Young;Park, Heon;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.375-378
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    • 2013
  • A reference voltage generator which is insensitive to PVT (process-voltage-temperature) variation necessary for NVM memory IPs such as EEPROM and MTP memories is designed in this paper. The designed BGR (bandgap reference voltage) circuit based on MagnaChip's $0.18{\mu}m$ EEPROM process uses a low-voltage bandgap reference voltage generator of cascode current-mirror type with a wide swing and shows a reference voltage characteristic insensitive to PVT variation. The minimum operating voltage is 1.43V and the VREF sensitivity against VDD variation is 0.064mV/V. Also, the VREF sensitivity against temperature variation is $20.5ppm/^{\circ}C$. The VREF voltage has a mean of 1.181V and its three sigma ($3{\sigma}$) value is 71.7mV.

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On-Chip CMOS Oscillator using PVT Compensated Circuit (공정, 전압, 온도 보상 회로를 이용한 On-Chip CMOS Oscillator)

  • Han, Do-Hee;Kwon, Ick-Jin
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.593-594
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    • 2008
  • In this article, process voltage temperature (PVT) compensated on-chip oscillator is implemented by using proportional to absolute temperature (PTAT) circuit and process compensator. Process compensator circuit based on current subtracter and PTAT circuit are proposed for compensation of oscillation frequency to cope with process variation and temperature variation. All circuit can operate in the range of $3.5{\sim}5\;V$ supply voltage. It can be applied to PVT insensitive low frequency clock reference generator.

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A Study on the Design of a Beta Ray Sensor for True Random Number Generators (진성난수 생성기를 위한 베타선 센서 설계에 관한 연구)

  • Kim, Young-Hee;Jin, HongZhou;Park, Kyunghwan;Kim, Jongbum;Ha, Pan-Bong
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.12 no.6
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    • pp.619-628
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    • 2019
  • In this paper, we designed a beta ray sensor for a true random number generator. Instead of biasing the gate of the PMOS feedback transistor to a DC voltage, the current flowing through the PMOS feedback transistor is mirrored through a current bias circuit designed to be insensitive to PVT fluctuations, thereby minimizing fluctuations in the signal voltage of the CSA. In addition, by using the constant current supplied by the BGR (Bandgap Reference) circuit, the signal voltage is charged to the VCOM voltage level, thereby reducing the change in charge time to enable high-speed sensing. The beta ray sensor designed with 0.18㎛ CMOS process shows that the minimum signal voltage and maximum signal voltage of the CSA circuit which are resulted from corner simulation are 205mV and 303mV, respectively. and the minimum and maximum widths of the pulses generated by comparing the output signal through the pulse shaper with the threshold voltage (VTHR) voltage of the comparator, were 0.592㎲ and 1.247㎲, respectively. resulting in high-speed detection of 100kHz. Thus, it is designed to count up to 100 kilo pulses per second.

Design of Low Power and High Speed NCL Gates (저전력 고속 NCL 비동기 게이트 설계)

  • Kim, Kyung Ki
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.2
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    • pp.112-118
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    • 2015
  • Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

Design of a 512b Multi-Time Programmable Memory IPs for PMICs (PMIC용 512비트 MTP 메모리 IP설계)

  • Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.9 no.1
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    • pp.120-131
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    • 2016
  • In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.