• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.3
• /
• pp.401-410
• /
• 2017

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.52 no.2
• /
• pp.74-79
• /
• 2003

The method of the analysis of the base Gummel number of the BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of NPN BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data and the transistor saturation current of PNP BJT shows an averaged relative error of 9.2% compared with the measured data

• Journal of Environmental Science International
• /
• v.7 no.4
• /
• pp.541-548
• /
• 1998

Aqueous phase adsorption of phenols by granular activated carbon was studied in a batch adsorption vessel. Adsorption Isotherms of phenol(Ph), p-chlorophenol(PCP) and p-nitrophenol (PNP) from aqueous solution on granular activated carbon have been obtained. The experimental data were analyzed by the surface and pore diffusion models. Both models could be applied to predict the adsorption phenomena. However, the pore diffusion model was slightly better than the surface diffusion model In representing the experimental data for the initial concentration changes. Therefore, the pore diffusion model was used to predict the change of operating variables such as the agitation speed and Particle size of adsorbent which have influence on the film resistance and intraparticle diffusion.

• Proceedings of the KIEE Conference
• /
• 2008.10b
• /
• pp.165-168
• /
• 2008

The experimental results of exposing IGBT (Insulated Gate Bipolar Transistor) samples to gamma radiation source show shifting of threshold voltages in the MOSFET and degradation of carrier mobility and current gains. At low total dose rate, the shift of threshold voltage is the major contribution of current increases, but for more than some total dose, the current is increased because of the current gain degradation occurred in the vertical PNP at the output of the IGBTs. In the paper, the collector current characteristics as a function of gate emitter voltage (VGE) curves are tested and analyzed with the model considering the radiation damage on the devices for gate bias and different dose. In addition, the model parameters between simulations and experiments are found and studied.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.9 no.5
• /
• pp.51-56
• /
• 1995

The transistors of single phase 3 level PWM Inverter compose output power transistors and neutral point clamping transistors, which are NPN transistors. Waveforms of driving signals for this are PWM waves for power transistors and period operating waves for neutral point clamping transistors, which signals made W-type modulation from rectangular and sine wave. The output power transistors operate at ON-time complementary and neutral point clamping transistors operate at OFF-time complementary respectively. Therefore, each transistors operate in half period at parallel. Characteristics of this inverter circuit is parallel switching method about series switching method of general inverter. As modulation of 3 level drive signals made from full-wave rectifier of sine wave and rectangular wave, which are level wave about 3 level of complementary transistor inverter. So, this circuit composed complementary operation inverter of NPN transistors only compare with PNP-NPN complementary inverter, which have high power 3 level inverter of complementary operation.

• The Magazine of the IEIE
• /
• v.24 no.6
• /
• pp.38-49
• /
• 1997

0.4mm Resign Rule의 Super Low Power Dissipation, Low Voltage. Operation-5- Full CMOS SRAM Cell을 개발하였다. Retrograde Well과 PSL(Poly Spacer LOCOS) Isolation 공정을 사용하여 1.76mm의 n+/p+ Isolation을 구현하였으며 Ti/TiN Local Interconnection을 사용하여 Polycide수준의 Rs와 작은 Contact저항을 확보하였다. p-well내의 Boron이 Field oxide에 침적되어 n+/n-well Isolation이 취약해짐을 Simulation을 통해 확인할 수 있었으며, 기생 Lateral NPN Bipolar Transistor의 Latch Up 특성이 취약해 지는 n+/n-wellslze는 0.57mm이고, 기생 Vertical PNP Bipolar Transistor는 p+/p-well size 0.52mm까지 안정적인 Current Gain을 유지함을 알 수 있었다. Ti/TiN Local Interconnection의 Rs를 Polycide 수준으로 낮추는 것은 TiN deco시 Power를 증가시키고 Pressure를 감소시킴으로써 실현할 수 있었다. Static Noise Margin분석을 통해 Vcc 0.6V에서도 Cell의 동작 Margin이 있음을 확인할 수 있었으며, Load Device의 큰 전류로 Soft Error를 개선할수 있었다. 본 공정으로 제조한 1M Full CMOS SRAM에서 Low Vcc margin 1.0V, Stand-by current 1mA이하(Vcc=3.7V, 85℃기준) 를 얻을 수 있었다.

• The Journal of Korean Physical Therapy
• /
• v.11 no.1
• /
• pp.137-141
• /
• 1999

Proprioceptive neuromuscular facilitation(PNF), pelvic patterns are very important for orthopaedic and neurologic patient. It is an essential treatment techniques for motor developmental disorder. CVA, lumbar disk, muscle weekness and pain control of lumbar, pelvic and lower extremity, Pelvic patterns of PNP has 4 different type of basic pattern. each of them is combinding of movement plane and functional movement. Biomechanically most of PNF patterns are a concentric contraction with third-class lever. But the movement pattern have a technique of combination of isotonic that should make a eccentric contraction with second-class lever.

• Journal of IKEEE
• /
• v.10 no.2 s.19
• /
• pp.141-148
• /
• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• Journal of IKEEE
• /
• v.10 no.2 s.19
• /
• pp.149-155
• /
• 2006

In this study, the design of low voltage DC-DC converter with low triggering ESD (Electro-Static Discharge) protection circuit was investigated. The purpose of this paper is design optimization for low voltage(2.5V to 5.5V input range) DC-DC converter using CMOS switch. In CMOS switch environment, a dominant loss component is not switching loss but conduction loss at 1.2MHz switching frequency. In this study a constant frequency PWM converter with synchronous rectifier is used. And zener Triggered SCR device to protect the ESD phenomenon was designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 8V.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.89-92
• /
• 2001

In this paper, a simple low-power CMOS current reference circuit is proposed. The reference circuit includes parasitic pnp BJTs and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a base-to-emitter voltage. The designed circuit has been simulated using a 0.25${\mu}{\textrm}{m}$ n-well CMOS process parameters. The simulation results show that the reference current is 34.96$mutextrm{A}$$\pm$0.04$mutextrm{A}$ in the temperature range of -2$0^{\circ}C$ to 12$0^{\circ}C$ The reference current varies less than 0.6% when the power supply voltage changes from 2.5V to 3.5V For $V_{DD=5V}$ and T=3$0^{\circ}C$ the power consumption is 520㎼ during normal operation but reduces to 0.l㎻ during power-down mode.