• Title/Summary/Keyword: PLL system

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Communication Performance Analysis and Characteristics of Frequency Synthesizer in the OFDM/FH Communication System (OFDM/FH 통신시스템에 사용되는 주파수 합성기의 특성과 통신 성능 분석)

  • 이영선;유흥균
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.8
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    • pp.809-815
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    • 2003
  • It is very important to get very high switching speed as well as low phase noise of frequency synthesizer in the OFDM/FH communication system. In this paper we compare the phase noises and switching speeds of the conventional PLL and digital hybrid PLL(DH-PLL) frequency synthesizer, also, we investigate the effect of phase noise on the performance of OFDM/FH communication system. DH-PLL has high switching speed property at the cost of circuit complexity and more power consumption. Unlike the conventional PLL in which the phase noise and switching speed have the trade off relationship in respect of loop filter bandwidth, DH-PLL frequency synthesizer can perform fast switching speed and low phase noise simultaneously. Under the condition of same hopping speed requirement, DH-PLL can achieve faster switching speed and lower SNR penalty compared with conventional PLL in the OFDM/FH communication system.

Speed control of induction motor for electric vehicles using PLL and fuzzy logic (PLL과 fuzzy논리를 이용한 전기자동차 구도용 유도전동기의 속도제어)

  • 양형렬;위석오;임영철;박종건
    • 제어로봇시스템학회:학술대회논문집
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    • 1997.10a
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    • pp.640-643
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    • 1997
  • This paper describes speed controller of a induction motor for electric vehicles using PLL and Fuzzy logic. The proposed system is combined precise speed control of PLL and robust, fast speed control of Fuzzy logic. The motor speed is adaptively incremented or decremented toward the PLL locking range by the Fuzzy logic using information of sampled speed errors and then is maintained accurately by PLL. The results of experiment show excellence of proposed system and that the proposed system is appropriates to control the speed of induction motor for electric vehicles.

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A study on the improvement of PLL system for three phase induction motor speed control (삼상유도전동기의 속도제어를 위한 PLL System의 개선에 관한 연구)

  • 정연택;이성용
    • 전기의세계
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    • v.30 no.12
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    • pp.832-837
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    • 1981
  • The study of PLL System to control the Speed of three phase induction motor is described. By solving some problems of conventional PLL system, the system has ability to be easily locked under any conditions. In order to study response velocity and stability of system, this paper presents different filter types and methods of determination of time constant.

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Flicker Noise Analysis in The Third-order of The PLL System (3차 PLL System에서의 Flicker Noise 분석)

  • 김형도;김경복;조형래
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.5
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    • pp.707-714
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    • 2000
  • In this paper, using third-order system of the PLL we'll analyze the aspect of flicker noise appearing troubles in the low frequency band. Since it is difficult to analyze mathematically flicker noise in the third-order system of the PLL, introducing the concept of pseudo-damping factor using the optimized second-filter has made an ease of the access of the flicker-noise variance. we'll show a numerical formula of flicker variance in the third-order system of the PLL which is compared with that of 1/f noise variance in the second-order system of the PLL.

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Flicker noise analysis in the third-order of the PLL system (3차 PLL SYSTEM에서의 flicker noise 분석)

  • 김형도;김경복;오용선;조형래
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1999.11a
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    • pp.230-235
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    • 1999
  • In this paper, Using third-order system of the PLL we analyze the aspect of flicker noise appearing troubles In the low frequency band. Since i. Is difficult to analyze mathematically flirter noise In the third-order system of the PLL, introducing the concept of pseudo-damping factor using the optimized second-filter makes an ease of the access of the flicker-noise variance. we'll show a numerical formula of flicker variance in the third-order system of the PLL which is compared with that of 1/f-noise variance in the second-order system of the PLL.

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Performance Analysis of DS/SS System with PLL Gain in the Multipath Fading Channel (다중경로 페이딩 채널하에서 PLL이득에 따른 DS/SS시스템의 성능분석)

  • Kang, Chan-Seok;Park, Jin-Soo
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.37 no.5
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    • pp.77-84
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    • 2000
  • In this paper, we modelized the multipath fading to Nakagami-m distribution fading channel which can be applied to the extended mobile communication channel environment. We assumed that the phase difference with reference signal happened in the received signal and in the receiver PLL(Phase Locked Loop) is the phase error. To correct the error we propose new RAKE receiver using PLL. In addition, we analyze the performance of DS/SS(Direct Sequence/spread Spectrum) system according to the gain of PLL,$\gamma_n$, the number of RAKE receiver branch L and MIP(Multipath Intensity Profile)'s exponential decay $\delta$. As a result, when the proposed RAKE receiver L Is increased and the $\delta$ is decreased the performance of the system gets better. Futhermore when PLL gain was 30dB, phase is identified. That is when the PLL gain is 30dB, the performance equals with the perfect coherent system's. Therefore, we can correct the phase error by using the proposed RAKE receiver and we proved that the PLL's requested limit gain should be 30dB.

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A Study on Low Phase Noise PLL Design for Ultra Wideband (초 광대역에 적용 가능한 저위상 잡음 PLL 설계에 관한 연구)

  • Shim, Yong-Sup;Lee, Il-Kyoo;Lee, Yong-Woo;Oh, Seung-Hyeub
    • Journal of Satellite, Information and Communications
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    • v.5 no.1
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    • pp.17-21
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    • 2010
  • In this paper, we have introduced a new way to design low phase noise PLL which can apply to the Ultra wideband as meeting performance requirements based on structure improvement, circuit supplement, upgraded design method. Before development of the PLL, we simulated spectrum power, phase noise, harmonic characteristic by using ADS(Advanced Designed System). And, we compared result between measurement and simulation. Finally, we confirm a satisfying result which meet performance requirements between required standard and measured value. It will be useful for transceiver of service which operate in Ultra wideband.

Design loop-filter for GHz-range charge-pump PLL (GHz급 charge-pump PLL응용을 위한 루프 필터 설계)

  • 정태식;전상오
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.11
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    • pp.76-85
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    • 1997
  • Charge-pump loop filter was designed using GaAs MESFET for GHz-range PLL system applications. Characteristics of charge-pump loop filter and stability of charge-pump PLL, system were analyzed. Performance specifications were defined and a charge-pump loop filter was designed that satisfies these specifications.

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Fuzzy PI-PLL Control for DC Motors

  • Kuc, Tae-Yong;Tefsuya, Muraoka
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.85.1-85
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    • 2001
  • A phase lock loop (PLL) circuit is a wellknown electronic circuit in communication engineering and other areas. In this paper, we present application of the PLL and fuzzy logic for DC motor control which are mixed well to be more effective for motor control. With this scheme, the control system can reach the set point rapidly, especially, it can eliminate noises. In addition, the PLL makes the system to have more stability; whereas, fuzzy logic controls helping PLL to be able to lock rapidly for a good response. The experiment result shows that the proposed control system works more efficacious. By performance comparison between the pure PLL control and the hybrid architecture of PLL with the fuzzy control, the result reveals the hybrid control ...

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Enhanced Dynamic Response of SRF-PLL System in a 3 Phase Grid-Connected Inverter (3상 계통연계형 인버터를 위한 SRF-PLL 시스템의 동특성 개선)

  • Choi, Hyeong-Jin;Song, Seung-Ho;Jeong, Seung-Gi;Choi, Ju-Yeop;Choy, Ick
    • The Transactions of the Korean Institute of Power Electronics
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    • v.14 no.2
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    • pp.134-141
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    • 2009
  • The new method is proposed to improve the dynamics of the phase angle detector during abrupt voltage dip caused by a grid fault. Usually, LPF(low pass filter) is used in the feedback loop of SRF(Synchronous Reference Frame) - PLL (Phase Locked Loop) system because the measured grid voltage contains harmonic distortions and sensor noises. A better transient response can be obtained with the proposed design method for SRF-PLL by the analysis of linearized model of the PLL system including LPF. Furthermore, in the proposed method, the controller gain and LPF cut-off frequency are changed from normal value to transient value when the voltage disturbance is detected. This paper shows the feasibility and the usefulness of the proposed methods through the computer simulation and the experiment.