• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.7
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• pp.1241-1249
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• 2007

Lately, many approaches of speed sensorless control method for Interior Permanent Magnet Synchronous Motor(IPMSM) ha, been developed. This paper proposes a novel sensorless algorithm for speed estimation of IPMSM. First of all, proposes sensorless method estimates flux of rotor using foundational voltage equation of IPMSM and then estimates position and speed of rotor using Phase Locked Loop(PLL). Proposed sensorless algorithm demonstrated through simulation using Matlab simulink and experiment.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1178-1185
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• 2009

In this paper, a wideband ultra-high speed & high purity discrete frequency synthesizer having minimum 2.5 MHz step size was proposed. To achieve fast and wideband operation, discrete frequencies were synthesized by mixing of 3 different pre-synthesized 16 frequencies made from fixed PLL and frequency dividers. Frequencies with discrete 2.5 MHz step were produced in 710~1,610 MHz. The measured hopping response time was 350 nsec average, output level was 21.5 dBm average with 2.65 dB flatness, spurious and harmonics level were suppressed below -60 dBc, and phase noise was -94 dBc/Hz@100 Hz. Also, a new measurement method for synthesizer response time was described.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1099-1106
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• 2018

In this paper, we developed and then analyzed the specifications of the frequency synthesizer which was applied to long range MFR (Multi-function Radar). These specifications were able to guarantee the functions and performance of MFR. MFR was the radar system that used phase array for electronically scanning. This frequency synthesizer made various frequency signals including to STALO (Stable Local Oscillator) for MFR. By analyzing the MFR requirements, we choose the optimal frequency synthesis method and then we got the best performance and functionality including to physical size for this system. We designed and fabricated DDS (Direct Digital Synthesizer)-driven Offset-PLL (Phase Locked Loop) synthesizer to meet the requirements which were low phase noise, fast switching time and low spurious. This synthesizer had less than -131dBc/Hz@100kHz phase noise and less than $4.1{\mu}s$ switching time, respectively.

• Journal of IKEEE
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• v.26 no.4
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• pp.577-583
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• 2022

Verilog-HDL-based modeling can be performed to confirm the fast operation characteristics after setting the design parameters of each block considering the stability of the system by performing linear phase-domain modeling on the phase-locked loop. This paper proposed Verilog-HDL modeling including DCO noise and DTC nonlinear characteristic. After completing the modeling, the time-domain transient simulation can be performed to check the feasibility and the functionality of the proposed PLL system, then the phase noise result from the system design based on the functional model can be verified comparing with the ideal phase noise graph. As a result of the comparison of simulation time (6 us), the Verilog-HDL-based modeling method (1.43 second) showed 484 times faster than the analog transistor level design (692 second) implemented by TSMC 0.18-㎛.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.1043-1049
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• 2005

In OFDM system suitable for high capacity high speed broadband transmission, ICI caused by phase noise degrades system performance seriously by destroying the orthogonality among subcarriers. In this paper, a new STFBC method combining ICI self cancellation scheme and antenna, time, frequency diversity is studied to reduce ICI effectively. CPE and ICI are analyzed by the phase noise linear approximation method in the proposed STFBC OFDM system. CIR, PICR and BER are discussed to compare the system performance degraded by phase noise of PLL. As results, STFBC method significantly reduces ICI. Furthermore, the SCI that usually happens in the traditional STBC, SFBC diversity coding method can be easily avoided.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.3
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• pp.128-133
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• 1998

This paper is study on performance analysis of modulator using direct digital frequency synthesizer of Initial Clock Accumulating Method. It has been generally used for PLL or digital frequency synthesizing method to be synthesizd randomly chosen frequency state. In order to improve disadvantage of two methods, we constructed modulator system using DDFS of Initial Clock Accumulating Method. We also confirmed the coherence frequency hopping state and possibility of phase control. The results obtained from the experiments are as follows; First, the synthesized output frequency is proportional to the sampling frequency, according to index, K. Second, the difference of the gain between the basic frequency and the harmonic frequencies was more than 50 [dB], that is, this means facts that is reduced the harmonic frequency factor. Third, coherence frequency hopping state is confirmed by PN code sequence. Here, we confirmed the proposed method cut switching time, this verify facts that is the best characteristic of the frequency hopping. We also verified the fact that the phase varies as the adder is operated set or reset.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.210-215
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• 2006

In this paper, we develop the PLL system of the local oscillator system using Gunn oscillator VCO for millimeter wave band receiving system. The local oscillator system consists of the $86{\sim}115GHz$ Gunn. diode oscillator part, the RF processing part including the diplexer and the harmonic mixer, and the DPLL system including Gunn modulator and controller. Based on this configuration, we verify the frequency and power stability of the developed local oscillator system. We developed system which applied to DPLL technique instead of the existing analog PLL method to accomplish this purpose. The developed system for this purpose is tested the frequency and power stability for a long time to confirm performance. Since we confirmed this system that had frequency characteristic of within ${\pm}10Hz$, very fine output drift power characteristic of $0.2{\sim}0.3dBm$ and about 200MHz locking range, it verified suitable for cosmic radio receiving system through the test result.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.13-22
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• 2001

This paper presents three dimensional structure of RF packages and the improvement effect of its electrical characteristics when implementing RF transceivers. We divided RF modules into several subunits following each subunit function based on the partitioning algorithm which suggests a method of three dimension stacking interconnection, PAA(pad area array) interconnection and stacking of three dimensional RF package structures. 224MHz ITS(Intelligent Transportation System) RF module subdivided into subunits of functional blocks of a receiver(RX), a transmitter(TX), a phase locked loop(PLL) and power(PWR) unit, simultaneously meeting the requirements of impedance characteristic and system stability. Each sub­functional unit has its own frequency region of 224MHz, 21.4MHz, and 450KHz~DC. The signal gain of receiver and transmitter unit showed 18.9㏈, 23.9㏈. PLL and PWR modules also provided stable phase locking, constant voltages which agree with design specifications and maximize their characteristics. The RF module of three dimension stacking structure showed $48cm^3$, 76.9％ reduction in volume and 4.8cm, 28.4％ in net length, 41.8$^{\circ}C$, 37% in maximum operating temperature, respectively. We have found that three dimensional PAA package structure is able to produce high speed, high density, low power characteristics and to improve its functional characteristics by subdividing RF modules according to the subunit function and the operating frequency, and the features of physical volume, electrical characteristics, and thermal conditions compared to two dimensional RF circuit modules.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.8 no.4
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• pp.38-45
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• 1994

It is very imprtant and necessary to predict luminous enviroment in an interior space. This paper has de scribed about energy saving and evaluated interior visual environment in a office building having on/off turning control lighting system utilizing daylight. In order to predict the interior varior illumination distribution, the scale model w a m~a de and examined under various conditions, such ad difference of window glass, and color pattern of wall, floor, and also ceiling lighting system type. Ths paper suggests that basic fundamental data of lighting design ~rformancein the concept and schematic stages of design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1543-1548
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• 2009

In this paper, a high speed code synchronization circuit is proposed. for fast code synchronization, matched filler method is used for initial code acquisition with two channel correlators. Particular frequency patterns of the limited number having the information about PN code start time are composed and transmitted repeatedly to increase the probability of accurate initial synchronization. And digital frequency synthesizer is proposed. And it's performance is analyzed theoretically. The analysis show that fast frequency hopping is possible in frequency hopping system that use digital frequency synthesizer.