• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.485-487
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• 2006

This paper describes a frequency synthesizer designed in a $0.25{\mu}m$ CMOS technology for using local oscillators for the IF stages. The design is focused mainly on low-power characteristics. A simple ring-oscillator based VCO is used, where a single control signal can be used for variable resistors. The designed PLL includes all building blocks for elimination of external components, other than the crystal, and its operating frequency can be programmed by external data. It operates in the frequency range of 250MHz to 800MHz and consumes l.08mA at 500MHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset. The die area is $1.09mm^2$

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.155-158
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• 1999

This paper describe the design and measurements of dual PLL for IMT-2000 cellular phone. As a result, dual PLL was well-operated in the RF frequency ranges of 2300 ~ 2360 MHz and If frequency of 380 MHz. The output power of -4.28 ㏈m, phase noise of -107.66㏈c/Hz at 100KHz frequency offset, lock time of 675.6$mutextrm{s}$ were obtained at 2330MHz. The output power of -4.78 ㏈m, phase noise of -115.28㏈c/Hz were also obtained at 380MHz.

• Journal of Advanced Marine Engineering and Technology
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• 제17권3호
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• pp.60-69
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• 1993

The speed control associated with dc servo motors for direct-drive applications of mobile robot is considered in this study. Robot is moved by power wheeled steering of two dc servo motors mounted to it. In order to cooperate with micro-computer and to achieve the high-performance operation of dc servo motor, speed control system is composed of a digital Phase Locked Loop and H-type drive circuit. And the motor is driven by Pulse Width Modulations. In controlling PWM, it is modified to compose of H-type drive circuit with feedback diodes and switching transistor and design of control sequence so that it may show linear characteristics. As a result, speed characteristics of motor showed linear features. In order to get data on design of PLL control system, the parameters of 80[W[ motor & robot device is measured by simple software control. The PLL speed control system is schemed and designed by leaner drive circuit and measured parameters. A complete speed control system applied to 80[W] dc servo motor showed good linearity, stability and high response. Also, it is verified that the PLL speed control system has good compatibility as a mobile robot driver.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• 한국정보통신학회논문지
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• 제13권11호
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• pp.2378-2384
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• 2009

본 논문에서는 $1{\mu}s$이하의 아주 짧은 위상고정시간을 가지는 새로운 방식의 위상고정루프(Phase Locked Loop, PLL)를 제안하였다. 지연고정루프(Delay Locked Loop, DLL)를 사용하여 입력 주파수를 체배 시켜 위상 고정 루프가 보다 더 높은 루프 대역폭을 가지도록 하여 위상고정이 짧은 시간에 일어나도록 설계하였다. 제안한 위상고정루프는 기존의 위상고정루프와 지연고정루프, 주파수 체배기로 구성되었으며 전원전압은 1.8V를 사용했다. $0.18{\mu}m$ CMOS 공정으로 Hspice를 이용해서 시뮬레이션 했으며 채널 변환 시 위상고정 시간은 $0.9{\mu}s$이다. 입력과 출력 주파수는 각각 162.5MHz, 2.6GHz이다.

• 전력전자학회논문지
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• 제13권6호
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• pp.447-452
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• 2008

본 논문은 단상 그리드전압의 동기화에 가장 적합한 곱형 PLL 시스템을 설계한다. 소신호 해석방법으로 PLL 시스템을 모델링하고, 동기 과도 응답특성뿐만 아니라 동기신호의 왜곡을 고려하여 저역필터의 차단주파수 및 이득의 최적 값을 유도한다. 설계의 성능을 검증하기 위하여, 시뮬레이션 및 실험결과로 차단주파수 및 이득의 변화에 동기신호의 과도응답과 리플성분을 관찰한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.1188-1191
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• 2003

In this paper, we focus our attention on the improvement of locking time and jitter parameter and propose the new structure of PLL which combined with the FVC, FOVI Matcher(FVC-Output and VCO-input Matching Circuit), Control Circuit and the conventional charge pump PLL. Using fast operation characteristics of the FVC, the circuit matching FVC-Output and VCO-input (FOVI Matcher) made to synchronize very fast. Fast locking time is usually required for application where the PLL has to settle rapidly if they switch from an idle mode to a normal mode and to track high-frequency data bit rate in data recovery systems. After a fast acqusition is achieved by the using the FVC, the conventional PLL operates for removing the phase error between the reference signal and the feedback signal. Therefore this structure can improve the trade-off between acquisition behavior and locked behavior.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.509-510
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• 2016

본 논문은 계통연계형 인버터의 위상추종기법인 SRF-PLL을 모델링하고, FPGA에 구현하기 위해 System Generator를 이용하여 설계하였다. SRF-PLL의 비례-적분 이득은 소신호 해석을 하여 일반화를 통해 입력전압의 크기에 관계없이 적용가능하며, 주파수 응답에서 65도 위상여유를 갖는 안정한 이득을 산정하였다. FPGA 구현을 위해 MATLAB/SIMULINK와 연동 가능한 System Generator를 이용하여 SRF-PLL을 모델링하였으며, MATLAB 기반의 시뮬레이션과 실험을 통하여 위상추종 특성을 분석하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2009년도 정기총회 및 추계학술대회 논문집
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• pp.302-304
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• 2009

Phase Locked Loop(PLL) 시스템은 UPS, 전력용 능동필터, PWM 정류기 등 여러 전력변환 장비에서 사용되어 왔다. 특히 계통에 연계된 능동 전력변환 시스템은 계통과의 동기화를 위해 위상각의 정확한 정보가 필요하며 PLL 시스템을 사용하여 측정한다. 실제 계통의 위상각과 추출된 위상각 사이의 오차는 기준 전류나 전압에 더 큰 고조파를 야기한다. 본 논문은 계통 고장에 강인한 PLL 시스템의 제어기를 제안한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.1132-1135
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• 2002

In this paper, we propose a phase-locked loop (PLL) with dual loops in which advantages of both loops can be combined. Frequency-locked loop (FLL) which is composed of two frequency-to-voltage converters (FVC) and an amplifier makes the frequency synchronize very fast and output signal is synchronized in phase with the input reference signal by charge pump PLL. This structure can improve the trade-off between acquisition behavior and locked behavior.