• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.191-200
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• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.82-86
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• 2009

This work is design of clock and data recovery circuit using system clock. This circuit is composed by PLL(Phase Locked Loop) to make system clock and data recovery circuit. The data recovery circuit using 1/4-rate phase picking Detector helps to reduce clock frequency. It is advantageous for high speed PLL. It can achieve a low jitter operation. The designed CDR(Clock and data recovery) has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and an active area $1{\times}1mm^2$.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.3
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• pp.19-25
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• 2000

In this paper, we describe RF receiver module for IMT-2000 handset with 5 MHz channel bandwidth. The fabricated RF receiver module consists of Low Noise Amplifier, RF SAW filter, Down-converter, If SAW filter, AGC and PLL Synthesizer. The NF and IIP3 of LNA is 0.8 dB, 3 dBm at 2.14 GHz, conversion gain of down-converter is 10 dB, dynamic range of AGC is 80 dB, and phase noise of PLL is -100 dBc at 100 kHz. The receiver sensitivity is -110 dBm, adjacent channel selectivity is 48 dBm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.675-677
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• 2009

통신기기에서 중요한 기술 중 하나인 PLL(Phase Locked Loop) 회로는 주기적인 신호를 원하는 대로, 정확한 고정점으로 잡아주는데 그 목적을 둔다. 일반적인 구조로 위상주파수검출기(Phase Frequency detector), 루프필터(Loop filter), 전압제어발진기(Voltage Controlled Oscillator), 디바이더(Divider)로 구성되어진다. 그러나 일반적인 PLL 구조로는 지터(jitter)가 증가하고 트랙(tracking) 속도가 느리다는 단점이 있다. 이를 보완하기 위해 루프필터 전단에 차지펌프(Charge pump) 회로를 추가하여 사용하고 있다. 본 논문에서는 CMOS를 이용한 PLL용 차지펌프를 설계하였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 Specter로 시뮬레이션 하였으며, Virtuso2로 레이아웃 하였다.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.137-140
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• 2005

A frequency synthesizer of 10 GHz $\sim$ 11 GHz for FMCW radar is designed and implemented by the form of indirect frequency synthesizer of a single loop structure. The synthesizer uses a high speed digital PLL chip. It is difficult to divide directly by using a program counter of PLL chip because the output frequency of VCO is 10 GHz $\sim$ 11 GHz, so we lower the frequency to 625 MHz $\sim$ 687.5 MHz by using a prescaler, and then divide the frequency by the program counter. The output frequency sweep of VCO from 10 GHz to 11 GHz is measured.

• Journal of Astronomy and Space Sciences
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• v.27 no.2
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• pp.145-152
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• 2010

In this paper, we developed a local oscillator (LO) system of millimeter wave band receiver for radio astronomy observation. We measured the phase and amplitude drift stability of this LO system. The voltage control oscillator (VCO) of this LO system use the 3 mm band Gunn oscillator. We developed the digital phase locked loop (DPLL) module for the LO PLL function that can be computer-controlled. To verify the performance, we measured the output frequency/power and the phase/amplitude drift stability of the developed module and the commercial PLL module, respectively. We show the good performance of the LO system based on the developed PLL module from the measured data analysis. The test results and discussion will be useful tutorial reference to design the LO system for very long baseline interferometry (VLBI) receiver and single dish radio astronomy receiver at the 3 mm frequency band.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.402-407
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• 2005

The PLL synthesizer is used in communication system until now because it have several merits, such as broad bandwidth, high accuracy and stability of frequency But it is difficult to use in the third generation mobile communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed the frequency synthesizer that generate frequencies randomly at a high speed using the DDS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1464-1469
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• 2001

본 논문에서는 디지털 하이브리드 위상고정루프(Digital Hybrid Phase-Locked Loop, DHPLL) 주파수 합성기 구조에서 고 순도 스펙트럼과 초고속 스위칭 속도를 위한 설계기술을 제안한다. D/A 변환기 출력으로 전압제어발진기(Voltage Controlled Oscillator, VCO)를 구동하는 개 루프(open-loop) 구성 방식과 기존 위상고정루프(Phase Locked Loop, PLL)의 폐 루프(closed-loop) 구성 방식을 혼합한 하이브리드 구조의 주파수 합성기를 고려하여, 시스템 변수(개 루프 대역과 위상 여유)와 성능 파라미터(정착시간, 위상 잡음, 그리고 최대 오버슈트(Max. overshoot)의 관계를 연구하였다. 그리고 이 관계를 통해 스펙트럼 순도와 스위칭 속도를 향상시키기 위한 최적의 3가지 설계방안을 제시한다. 컴퓨터 시뮬레이션 결과, 주파수 스위칭 과정에서 발생하는 최대 오버슈트가 0.0991%이고 완전 정상상태 도달시간은 0.288msec이다. offset 주파수 10KHz에서 위상 잡음은 -128.15dBc이다.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.697-699
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• 1999

2기가비트급 이상의 Serial-Link Chip에 적용되는 PLL의 특성은 lock-in-time이 빨라야하며 low VDD 동작을 확보해야 한다. 본 논문은 2.8기가비트급의 인터페이스 전송칩에 사용되는 PLL에 내부 전원 공급기를 설계하여 외부전원 3.3V시에 2.5V를 제공하며 이를 PFD/CP/VCO에 개별적 적용하는 제어방법 및 회로를 제안하며 이에 따르는 IPLL의 Lock-In-Time을 1mS 이내로 설계하였으며 외부동작 주파수는 100MHz이상이며 인터페이스 전송량은 2.8기가비트에 이른다. 저전압 설계를 통한 동작전류를 내부 전원 제어를 통해 순차적(Sequential Method)동작을 시킴으로 IPLL 동작시의 전류소모을 2mA이하로 제한하였다. 본 논문에서는 2.8기가비트급 인터페이스 전송칩에 적용한 IPLL의 회로 및 내부전원 공급기의 제어 방법 및 설계결과를 제안하며 이에 따르는 전송칩의 동작방법을 제안한다.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.718-720
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• 1999

This paper describes a charge pump PLL architecture which achieves high frequency operation and fast acquisition. This architecture employs multi-phase frequency detector comprised of precharge type phase frequency detector and conventional phase frequency detector. Operation frequency is increased by using precharge type phase frequency detector when the phase difference is small and acquisition time is shortened by using conventional phase frequency detector and increased charge pump current when the phase difference is large. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 694MHz at 3.0V and faster acquisition were achieved by simulation.