• Journal of Power Electronics
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• v.17 no.5
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• pp.1231-1243
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• 2017

Grid-interactive power converters are normally synchronized with the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations and the dc offsets in single-phase systems. In this paper, a single-phase PLL is presented to mitigate the effects of these non-idealities. This PLL is based on the popular second order generalized integrator (SOGI) structure. The SOGI structure is modified to eliminate the effects of input dc offsets. The resulting SOGI structure has a high-pass filtering property. Hence, this PLL is termed as a high-pass generalized integrator based PLL (HGI-PLL). It has fixed parameters which reduces the implementation complexity and aids in the implementation in low-end digital controllers. The HGI-PLL is shown to have the lowest resource utilization among the SOGI based PLLs with dc cancelling capability. Systematic design methods are evolved leading to a design that limits the unit vector THD to within 1% for given non-ideal input conditions in terms of frequency deviation and harmonic distortion. The proposed designs achieve the fastest transient response. The performance of this PLL has been verified experimentally. The results agree with the theoretical prediction.

• Journal of information and communication convergence engineering
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• v.3 no.1
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• pp.18-22
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• 2005

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.23-36
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• 2005

PLLs have been widely used for many applications including communication systems. This paper presents a VCO with an improved negative skewed delay scheme and a PLL using this VCO. The proposed VCO and PLL are intended for replacing traditional LC oscillators and PLLs used in communication systems and other applications. The circuit designs of the VCO and PLL are based on 0.18um CMOS technology with 1.8V supply voltage. The proposed VCO employs subfeedback loops using pass-transistors and needs two opposite control voltages for the pass transistors. The subfeedback loops speed up oscillation depending on the control voltages and thus provide a high oscillation frequency. The two voltage controls have opposite frequency gain characteristics and result in low phase-noise. The 7-stage VCO in 0.18um CMOS technology operates from $3.2GHz\~6.3GHz$ with phase noise of about -128.8 dBc/Hz at 1MHz frequency onset. For 1.8V supply voltage, the current consumption is about 3.8mA. The proposed PLL has dual loop-filters for the proposed VCO. The PLL is operated at 5GHz with 1.8V supply voltage. These results indicate that the proposed VCO can be used for radio frequency operations replacing LC oscillators. The circuits have been designed and simulated using 0.18um TSMC library.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.711-717
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• 2017

This paper proposes an improved sensorless control to estimate the rotor position of an interior permanent magnet synchronous motor. A phase-locked loop (PLL) is used to obtain the phase angle of the grid. The rotor position can be estimated using a PLL based on extended electromotive force (EEMF) because the EEMF contains information about the rotor position. The proposed method can reduce the burden of calculation. Therefore, the control period is decreased. The simulation and experimental results confirm the effectiveness and performance of the proposed method.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.403-405
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• 1996

This paper suggestes a SRM drive scheme which include power angle control like synchronous machine and a Phase Locked LooP(PLL) control. The power angle control scheme regulates instantly dwell angle as load torque variation, but this is some disadvantages which are losing of synchronism and hunting when load changes abruptly. To increasing synchronism, the Phase Locked Loop control scheme is adopted.

• Proceedings of the KIPE Conference
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• 2001.12a
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• pp.185-189
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• 2001

This paper presents a precision voltage control technique of a single phase PWM inverter for a constant voltage and constant frequency(CVCF) applications. The proposed control employes a PLL compensating loop which minimize the steady state error and phase delay. The computer simulation and experiment are carried out for the actual single phase PWM inverter and the results well demonstrate the effectiveness of the proposed control.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.985-987
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• 2004

Switched Reluctance Motor(SRM) drive system is known to provide good torque characteristics and high efficiency drive. However, speed variation caused by higher torque ripple is one of main drawback. The Phase-Locked Loop (PLL) technique in conjunction with dynamic dwell angle control has good speed regulation characteristics. In this paper, appropriate advance angle control for high efficiency drive and PLL technique for accurate speed control is proposed. A TMS320F240 DSP is used to realize this drive system. Test results show that the system has good dynamic and precise speed control ability as well as high efficiency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.888-894
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• 1986

In this paper, a phase locked loop control system is designed to have high performance and stability in a 2-phase bifilar winding PM step motor. The BODE diagram analysis method is used to improve the stability and dynamic characteristic of the closed loop control system. Also, a PLL servo is used to accomplish high-precision speed and to attain smooth ness. In applying the PLL control to the step motor, a new design method is suggested to solve the control problem which occurs as a result of the limited maximum acceleration of the step motor. A simple design method is suggested without using the complicated multi-step characteirstic of the step motor in constant voltage driving. Computer simulation results agree clorelg with experiments, indicating that the PLL servo system of the step motor designed is very useful.

• The Transactions of the Korean Institute of Power Electronics
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• v.2 no.3
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• pp.20-25
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• 1997

SRM은 많은 장점으로 인해 각종 산업분야에 적용을 검토하고 있다. 그러나 토오크리플과 소음이 교류전동기보다 상대적으로 높은 단점이 있다. SRM은 상전류파형이 동작특성과 토오크리플발생에 큰 영향을 미친다. 본 논문에서는 토오크리플을 줄이고 정밀한 속도제어를 위해 순시도통각제어와 PLK제어시스템을 이용하였다. PLL의 위상검출기는 도통각제어에, 루우프필터의 출력은 순시 인가전압의 제어에 각각 도입하여 속응성을 높이고 토오크리플을 줄일 수 있도록 하였다. 실험을 통하여 정밀한 속도제어와 토오크리플 저감특성을 확인할 수 있었다.

• Journal of Power Electronics
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• v.15 no.1
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• pp.65-77
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• 2015

Resonant converters are well suited for induction heating (IH) applications due to their advantages such as efficiency and power density. The control systems of these appliances should provide smooth and wide power control with fewer losses. In this paper, a simple phase locked loop (PLL) based variable duty cycle (VDC) pulse density modulation (PDM) power control scheme for use in class-D inverters for IH loads is proposed. This VDC PDM control method provides a wide power control range. This control scheme also achieves stable and efficient Zero-Voltage-Switching (ZVS) operation over a wide load range. Analysis and modeling of an IH load is done to perform a time domain simulation. The design and output power analysis of a class-D inverter are done for both the conventional pulse width modulation (PWM) and the proposed PLL based VDC PDM methods. The control principles of the proposed method are described in detail. The validity of the proposed control scheme is verified through MATLAB simulations. The PLL loop maintains operation closer to the resonant frequency irrespective of variations in the load parameters. The proposed control scheme provides a linear output power variation to simplify the control logic. A prototype of the class-D inverter system is implemented to validate the simulation results.