• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.449-454
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• 2005

Brushless DC Motor(PM BLDCM) is widely used in industrial applications due to its high efficiency and power density. In order to increase reliability and reduce system cost, this paper studies particularly applicable method for sensorless PM BLDCM drive system. The resulting third harmonic signal keeps a constant phase relationship with the rotor flux for any motor speed and load condition, and is practically free of noise that can be introduced by the inverter switching, making this a robust sensing method. As a result, the method described here is not sensitive to filtering delays, allowing the motor to achieve a good performance over a wide speed range. In addition, a simple starting method and a speed estimation approach are also proposed.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.684_685
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• 2009

A digital sampling algorithm that uses a two high resolution integrating Voltmeters which are synchronized by Phase Lock Loop (PLL) time clock for accurately measuring the parameters, active and reactive power, for sinusoidal power measurements is presented. The PLL technique provides high precision measurements, root mean square (rms), phase and complex voltage ratio, of the AC signal. The system has been designed to be used at the Korean Research Institute of Standards and Science (KRISS) as a reference power standard for electrical power calibrations. The test results have shown that the accuracy of the measurements is better than $10 {\mu}W/VA$ and the level of uncertainty is valid for the power factor range zero to 1 for both lead and lag conditions. The system is fully automated and allows power measurements and calibration of high precision wattmeters and power calibrators at the main power frequencies 50 and 60 Hz.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2350-2352
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• 2004

This paper presents the implementation-tation of the real-time software GPS Receiver based on FFT and FLL assisted PLL tracking algorithm. The FFT(fast fourier transform) based GPS si-gnal acquisition scheme provides a fast TTFF(time to first fix) performance. The tracking based on FLL assisted PLL enables tracking of GPS signal in a high dynamic environment. The designed software GPS receiver uses the indexing method for generating replica carrier to reduce computation load. The performance of the implemented GPS receiver is evaluated using high-dynamic simulated data from a simulator and real static data.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.687-694
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• 1999

In this paper, to draw out the parameter of synchronization for ADSL(Asymmetric Digital Subscriber Line) chip design, we analyze the performance of STR(Symbol Timing Recovery) and frame synchronization with computer simulation. We analyze and design PLL(Phase Lock Loop) loop for ADSL. As a result, we obtained the optimum parameter of STR to design ADSL chip. Also, when performed frame synchronization with several algorithm, we analyzed the performance of FER(Frame Error Rate) and the effect of frame offset with computer simulation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.63-68
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• 2014

This paper related with the I-CMA (Improved-CMA) algorithm that is possible to compensates of phase in CMA adatpve equalizer which is used for the elemination of intersymbol interference in the multipath fading and band limit characteristics of channel. The new cost function is proposed for the eliminate the amplitude and phase simulataneous by modifying the cost fuction for get the error signal in present CMA algorithm. It has a merit to the algorithm simplicities and eliminats the PLL device for phase compensation after equalization. For proving this, the recovered signal constellation that is the output of equalizer output signal and the residual isi and Maximum Distortion charateristic learning curve that are presents the convergence performance in the equalizer and the overall frequency transfer function of channel and equalizer were used. As a result of computer simulation, the I-CMA has more good compensation capability of amplitude and phas in the recovered constellation. But the convergence time is slow due to the simultaneously phase compensation.

• Proceedings of the KSR Conference
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• 2004.10a
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• pp.1480-1485
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• 2004

In this paper, a real-time digital kalman filtering algorithm is used to obtain the reference estimation of the control current for shunt active power filter. This algorithm provides the best estimate of the fundamental and harmonic frequency components from the sampled values of the line current or voltage waveform. By adopting of the digital Kalman filtering algorithm, the structure of the control algorithm eliminates the need of a Phase locked loop(PLL) for the synchronization of the reference signal used in the compensation and it not sensitive to the distortion of the line voltage. The effectiveness of the algorithm is confirmed by the computer simulations.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• Proceedings of the KIEE Conference
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• 2004.10a
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• pp.224-226
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• 2004

Digital Kalman filter is presented as a powerful approach to obtain the reference estimation of the control current for shunt active power filter. This algorithm provides the best estimate of the fundamental and harmonic frequency components from the sampled values of the line current or voltage. By adopting of the digital Kalman filtering algorithm, the structure of the control algorithm eliminates the need of a Phase locked loop(PLL) for the synchronization of the reference signal used in the compensation and it not sensitive to the distortion of the line voltage. The effectiveness of the algorithm is confirmed by the computer simulations.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.15-22
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• 2006

This paper presents a novel signal tracking algorithm for GNSS receivers using a MLE technique. In order to perform a robust signal tracking in severe signal environments, e.g., high dynamics for navigation vehicles or weak signals for indoor positioning, the MLE based signal tracking approach is adopted in the paper. With assuming white Gaussian additive noise, the cost function of MLE is expanded to the cost function of NLSE. Efficient and practical approach for Doppler frequency tracking by the MLE is derived based on the assumption of code-free signals, i.e., the cost function of the MLE for carrier Doppler tracking is used to derive a discriminator function to create error signals from incoming and reference signals. The use of the MLE method for carrier tracking makes it possible to generalize the MLE equation for arbitrary codes and modulation schemes. This is ideally suited for various GNSS signals with same structure of tracking module. This paper proposes two different types of MLE based tracking method, i.e., an iterative batch processing method and a non-iterative feed-forward processing method. The first method is derived without any limitation on time consumption, while the second method is proposed for a time limited case by using a 1st derivative of cost function, which is proportional to error signal from discriminators of conventional tracking methods. The second method can be implemented by a block diagram approach for tracking carrier phase, Doppler frequency and code phase with assuming no correlation of signal parameters. Finally, a state space form of FLL/PLL/DLL is adopted to the designed MLE based tracking algorithm for reducing noise on the estimated signal parameters.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.512-515
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• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.