• Proceedings of the KIEE Conference
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• 2003.10b
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• pp.216-219
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• 2003

The resonant inverter is widely used for induction heating, electronic ballast and supersonic motor driving circuit. In the meantime, control techniques of PWM, PFM etc.. are mainly applied to control the output power of the resonant inverter. But, in the case of using the half bridge resonant inverter, it is difficult to control the output power by PWM, because its main circuit does not provide the load free-wheeling mode. Therefore, PAM or PFM was usually applied to control output power of half bridge resonant inverter. However, PAM needs a variable DC voltage source, which makes the system structure more complex. On the other hand, in case of PFM, efficiency is declined by operation with poor power factor. This paper Proposed the novel half bridge resonant inverter which can provide the load free-wheeling mode. Also its analysis results for PWM operation with unity fundamental power factor are Presented and compared with other resonant inverters using PWM and PFM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.1-9
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• 2008

This paper suggests the triple-mode CMOS DC-DC converter that has temperature/voltage variation compensation techniques. The proposed triple-mode CMOS DC-DC converter is used to generate constant or variable voltages of 0.6-2.2V within battery source range of 3.3-5.5V. Also, it supports triple modes, which include Pulse Width Modulator (PWM) mode, Pulse Frequency Modulator (PFM) mode and Low Drop-Out (LDO) mode. Moreover, it uses 1MHz low-power CMOS ring oscillator that will compensate malfunction of chip in temperature/voltage variation condition. The proposed triple-mode CMOS DC-DC converter, which generates output voltages of 0.6-2.2V with an input voltage sources of 3.3-5.5V, exhibits the maximum output ripple voltage of below 10mV at PWM mode, 15mV at PFM mode and 4mV at LDO mode. And the proposed converter has maximum efficiency of 93% at PWM mode. Even at $-25{\sim}80^{\circ}C$ temperature variations, it has kept the output voltage level within 0.8% at PWM/PFM/LDO modes. For the verification of proposed triple-mode CMOS DC-DC converter, the simulations are carried out with $0.35{\mu}m$ CMOS technology and chip test is carried out.

• 전자공학회논문지 IE
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• v.47 no.3
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• pp.14-18
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• 2010

In this paper, we describe a CMOS DC-DC converter with a variable output voltage(5-7V @100mA) for a portable battery-operated system applications. The proposed DC-DC converter is used along with a Pulse-Frequency Modulation (PFM) method and consists of reference circuit, a feedback resistor, a controller, and an internal oscillator. The integrated DC-DC converter with two external passive components(L,C) has been designed and fabricated on a 0.5um 2-poly 3-metal CMOS process and could be applied to the Personal Digital Assistants(PDA), cellular Phone, Laptop Computer, etc.

• Journal of IKEEE
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• v.15 no.4
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• pp.319-323
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• 2011

In this paper presents a new model of dual-mode synchronous buck converter with dynamic control for mobile applications was proposed. The proposed circuit can operate at 2.5MHz with supply voltage 2.5V to 5V for low ripple and minimum inductor and capacitor size, which is suitable for single-cell lithium-ion battery supply mobile applications. For high efficiency, the proposed circuit adopts synchronous type and dynamic control. The proposed circuit is designed by using the device parameter of TSMC 0.18um BCD process and the performance is evaluated by Cadence spectre. Experimental board level results show the maximum conversion efficiency is 96% at 100mA load current.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.601-602
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• 2008

This paper presents pulse-frequency modulation(PFM) to improve the light-load efficiency. The proposed circuit is designed by using the device parameter of standard $0.13{\mu}m$ CMOS process. The performance of proposed circuit is evaluated by HSPICE simulation Measured efficiency in a light-load is measured 78-90 % for 0.1 to 100mA output current.

• The Journal of Advanced Prosthodontics
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• v.12 no.4
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• pp.181-188
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• 2020

PURPOSE. The effect of core design on the fracture resistance of zirconia-lithium disilicate (LS2) bilayered crowns for anterior teeth is evaluated by comparing with that of metal-ceramic crowns. MATERIALS AND METHODS. Forty customized titanium abutments for maxillary central incisor were prepared. Each group of 10 units was constructed using the same veneer form of designs A and B, which covered labial surface to approximately one third of the incisal and cervical palatal surface, respectively. LS2 pressed-on-zirconia (POZ) and porcelain-fused-to-metal (PFM) crowns were divided into "POZ_A," "POZ_B," "PFM_A," and "PFM_B" groups, and 6000 thermal cycles (5/55 ℃) were performed after 24 h storage in distilled water at 37 ℃. All specimens were prepared using a single type of self-adhesive resin cement. The fracture resistance was measured using a universal testing machine. Failure mode and elemental analyses of the bonding interface were performed. The data were analyzed using Welch's t-test and the Games-Howell exact test. RESULTS. The PFM_B (1376. 8 ± 93.3 N) group demonstrated significantly higher fracture strength than the PFM_A (915.8 ± 206.3 N) and POZ_B (963.8 ± 316.2 N) groups (P<.05). There was no statistically significant difference in fracture resistance between the POZ_A (1184.4 ± 319.6 N) and POZ_B groups (P>.05). Regardless of the design differences of the zirconia cores, fractures involving cores occurred in all specimens of the POZ groups. CONCLUSION. The bilayered anterior POZ crowns showed different fracture resistance and fracture pattern according to the core design compared to PFM.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1627-1633
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• 2018

A constant voltage AC-DC converter based on digital assistant technology is proposed in this paper, which has rapid dynamic response capability. The converter operates in the PFM (Pulse Frequency Modulation) mode. According to the load state, the compensation current produced by the digital compensation module was injected into the CS pin to adjust the switching pulse width dynamically and improve the dynamic response. The control chip is implemented based on NEC $1{\mu}m$ 5V/40V HVCMOS process. A 5V/1.2A prototype has been built to verify the proposed control method. When the load jumps from idle to heavy, the undershoot time is only 7.4ms.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.40-47
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• 2016

In this paper, a dual mode buck converter with an ability to change mode is proposed, which is suitable particularly for portable device. The problem of conventional mode control circuit is affected by load variation condition such as suddenly or slowly. To resolve this problem, the mode control was designed with slow clock method. Also, when change from the PFM(Pulse Frequency Modulation) mode to the PWM(Pulse Width Modulation) mode, to use the counter to detect a high load. And the user can select mode transition point in load range from 20mA to 90mA by 3 bit digital signal. The circuits are implemented by using BCDMOS 0.18um 2-polt 3-metal process. Measurement environment are input voltage 3.7V, output voltage 1.2V and load current range from 10uA to 500mA. And measurement result show that the peak efficiency is 86% and ripple voltage is less 32mV.

• Journal of Power Electronics
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• v.12 no.6
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• pp.886-894
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• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1425-1427
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• 2005

In this paper, with loosely coupled transformer series-parallel resonant type DC/DC converter is analyzed. To get more efficient operating mode of the series-parallel resonant type DC/DC converter, theoretical analysis using normalized parameters are accepted. The proposed converter must be operated in Pulse Frequency Modulation(PFM) switching pattern for the Zero Voltage Switching(ZVS) operation. According to PFM control method, the output voltage of the proposed circuit can be controlled.