• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.557-561
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• 2001

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integraded circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding 1㎛ in size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particles agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectrics(IMD)-CMP process. The filter installation in CMP polisher could reduce defects after IMD-CMP process. As a result of micro-scratch formation, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. We have concluded that slurry filter lifetime is fixed by the degree of generating defects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.364-365
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• 2005

This paper report nanotribological behavior between Si tip and Cu wafer surfaces which was treated various concentration of $H_2O_2$. This experimental approach has proven atomic level insight into Cu CMP. It has been used to study interfacial friction and adhesion force between Si tip and Cu wafer surfaces in air by atomic force microscopy (AFM). Adhesion force of Cu surfaces which was pre-cleaned in diluted HF solution was lager than Cu oxide surfaces. Adhesion force of Cu oxide surface was saturated around 7 nN. Slope of normal force vs lateral signal was increased as increasing concentration of $H_2O_2$ and it was saturated around 24. Friction force of Cu oxide was lager than Cu.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.838-843
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• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.59-59
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• 2009

현재 CMP분야는 광역 평탄화 반도체 소자의 집적화 및 소형화가 진행됨에 따라서 CMP 공정의 중요성은 날로 성장하고 있다. 하지만 이러한 CMP공정은 불가피하게도 scratch, pit, CMP residue와 같은 defect들을 발생시키고 있으며, 점점 선폭이 작아짐에 따라, 이러한 defect들이 반도체 수율에 미치는 영향은 심각해지고 있다. Defect들 중에 특히 scratch는 반도체에 치명적인 circuit failure를 일으키게 된다. 또한 반도체 내구성과 신뢰성을 감소시키게 되고, 누전전류를 증가시키는 등 바람직하지 못한 현상들이 생기게 된다. 본 연구에서는 scratch 와 같은 deflect들을 효율적으로 검출, 분석하고, scratch를 감소시키는데 그 목적이 있다. 본 실험을 위해 8" TEOS wafer와 commercial oxide slurry 및 friction polisher (Poli-500, G&P tech., Korea)를 사용하여 CMP 공정을 진행하였으며, CMP 공정조건은 각각 80rpm/80rpm/1psi(Platen speed/Head speed/Pressure)에서 1분 동안 연마를 한 후 scratch 발생 경향을 살펴보았다. CMP 후 wafer위에 오염되어 있는 slurry residue들을 제거하기 위해 SC-1, HF 세정을 이용하여 최적화된 post-CMP 공정기술을 제안하였다. Scratch 검출 및 분석을 위해 wafer surface analyzer (Surfscan 6200, Tencor, USA)와 optical microscope (LV100D, Nicon, Japan)를 사용하였다. CMP 공정 변수들에 따른 scratch 발생정도를 비교하였으며, scratch 발생 요인들에 따른 scratch 형태 및 발생정도를 살펴보았다. 최적화된 post-CMP 세정 조건은 메가소닉과 함께 SC-1 세정을 실시하여 slurry residue들을 제거한 후, HF 세정을 실시하여 잔여 오염물들을 제거하고 검출이 용이하도록 scratch를 확장시킬 수 있도록 제안하였으며, 100%의 particle removal efficiency (PRE)를 얻을 수 있었다. 실제 CMP 공정후 post-CMP 세정 단계별 scratch 개수를 측정한 결과, SC-1 세정 후 약 220개의 scratch가 검출되었으며, 검출되지 않았던 scratch가 HF 세정 후 확장되어 드러남에 따라 약 500개의 scratch 가 검출되었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.149-153
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• 2003

Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between $SiO_2$ and $Si_3N_4$ films for the purpose of process simplification and n-situ end point detection(EPD). However, STI-CMP process has various defects such as nitride residue, tom oxide and damage of silicon active region. To solve these problems, in this paper, we studied the planarization characteristics using a high selectivity slurry(HSS). As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of HSS STI-CMP process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.527-527
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• 2007

CMP가 1980년 IBM에 의해 반도체 웨이퍼의 표면 연마를 위해 적용된 후, 많은 연구 개발의 노력으로 반도체 집적회로의 제조 공정에서 필수 핵심기술이 되었으나, 소모자재(연마패드, 탄성지지대, 슬러리, 패드 컨디셔너)의 비용이 CMP 공정 비용의 70% 이상을 차지하는 등 제조단가가 높다는 단점을 극복할 수가 없었다. 특히, 고가의 슬러리가 차지하는 비중이 40% 이상을 넘고 있어, 슬러리 원액의 소모량을 줄이기 위한 연구들이 현재 활발히 연구 중이다. 슬러리의 변수로는 연마입자의 종류 및 특성, 용액의 pH, 연마입자의 슬러리내 안정성 등이 있다. 슬러리내 연마입자는 연마량과 균일도 측면에서 밀접한 관계를 가지고 있다. 또한, 연마제의 영향에 따라 연마율의 차이 즉, CMP 특성의 변화를 보이고 있기 때문에 투입량 또한 최적화가 필요하다. 본 연구에서는 새로운 연마제의 특성을 알아보기 위해 탈이온수(de-ionized water; DIW)에 $CeO_2,\;MnO_2,\;ZrO_2$ 등을 첨가한 후 분산시간에 따른 연마 특성과 atomic force microscopy (AFM)분석을 통해 표면 거칠기를 비교 분석하였다. 그리고, 세 가지 종류의 연마제를 각각 1wt%, 3wt%, 5wt% 첨가하여 산화막에 대한 CMP 특성을 알아본 후, scanning electron microscopy (SEM) 측정과 입도 분석을 통해 그 가능성을 알아보았다.

• Transactions on Electrical and Electronic Materials
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• v.8 no.1
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• pp.1-4
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• 2007

This paper discusses two approaches for pre-polishing optimization of oxide chemical mechanical planarization (CMP) that can be used as alternatives to the commonly applied dummy structure insertion in shallow trench isolation (STI) and replacement gate (RG) technologies: reverse nitride masking (RNM) and oxide etchback (OEB). Wafers have been produced using each optimization technique and CMP tests have been performed. Dishing, erosion and global planarity have been investigated with the help of conductive atomic force microscopy (C-AFM). The results demonstrate the effectiveness of both techniques which yield excellent planarity without dummy structure related performance degradation due to capacitive coupling.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.542-542
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• 2008

본 논문에서는 기존에 상용화된 슬러리에 비해 새로운 혼합 연마제 슬러리의 우수성을 입증하고, 최적화 된 공정기술을 연구의 기반으로 활용하고자 Silica slurry에 $CeO_2$ 연마제를 혼합하여, 어떠한 연마 특성을 나타내는지 알아보았고, AFM, EDX, XRD, TEM 분석을 통해 그 가능성을 비교 분석하였다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.122-125
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• 2003

We investigated the effect of the abrasive and additive concentrations in Nano ceria slurry on the pad surface temperature under varying pressure through chemical mechanical polishing (CMP) test using blanket wafers. The pad surface temperature after CMP increased with the abrasive concentration and decreased with increase of the additive concentration in slurries for the constant down pressure. A possible mechanism is that the additive adsorbed on the film surface during polishing decreases the friction coefficient, hence the pad surface temperature gets lower with increase of the additive concentration. This difference of temperature was more remarkable for the higher concentration of abrasives. In addition, in-situ measurement of spindle motor was carried out during oxide and nitride polishing. The averaged motor current for oxide film was higher than that for nitride film, which means the higher friction coefficient.

• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.1
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• pp.28-32
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• 2003

In this paper, we have studied the in-situ end point detection (EPD) for direct chemical mechanical polishing (CMP) of shallow trench isolation (STI) structures without the reverse moat etch process. In this case, we applied a high selectivity $1n (HSS) that improves the silicon oxide removal rate and maximizes oxide to nitride selectivity Quite reproducible EPD results were obtained, and the wafer-to-wafer thickness variation was significantly reduced compared with the conventional predetermined polishing time method without EPD. Therefore, it is possible to achieve a global planarization without the complicated reverse moat etch process. As a result, the STI-CMP process can be simplified and improved using the new EPD method.