• Journal of electromagnetic engineering and science
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• v.7 no.2
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• pp.64-68
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• 2007

An InGaP/GaAs HBT based differential Colpitts voltage control oscillator(VCO) is presented in this paper. In the VCO core, two switching transistors are introduced to steer the core bias current to save power. An LC tank with an inductor quality factor(Q) of 11.4 is used to generate oscillation frequency. It has a superior phase noise characteristics of -130.12 dBc/Hz and -105.3 at 1 MHz and 100 kHz frequency offsets respectively from the carrier frequency(1.566 GHz) when supplied with a control voltage of 0 volt. It dissipates output power of -5.3 dBm. Two pairs of on-chip base collector (BC) diodes are used in the tank circuit to increase the VCO tuning range(168 MHz). This VCO occupies the area of $1.070{\times}0.90mm^2$ including buffer and pads.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.336-343
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• 2011

This paper introduces a simple variable gain amplifier (VGA) structure that shows an inherently dB-linear gain control property. Requiring no additional components for dB-linear control, the structure is compact and power efficient. The designed two-stage VGA shows a gain control range of 60dB with the gain error in the range of ${\pm}0.4$ dB. The power consumption including the output buffer is 20.4 mW from 1.2 V supply voltage with bandwidth of 630 MHz. The prototype was fabricated in a 0.13 ${\mu}m$ CMOS process and the VGA core occupies 0.06 $mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.4
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• pp.421-427
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• 2004

A low cost solution employing harmonic oscillation to the frequency synthesizer at 5.8 ㎓ is proposed. The proposed frequency synthesizer is composed of 2.9 ㎓ PLL chip, 2.9 ㎓ oscillator, and 5.8 ㎓ buffer amplifier The measured data shows a frequency Outing range of 290 ㎒, ranging from 5.65 to 5.94 ㎓ about 0.5 ㏈m of output power, and a phase noise of -107.67 ㏈c/㎐ at the 100 ㎑ offset frequency. All spurious signals including fundamental oscillation power(2.9 ㎓) are suppressed at least 15 ㏈c than the desired second harmonic signal.

• Journal of Korean Institute of Industrial Engineers
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• v.22 no.3
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• pp.313-324
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• 1996

A new policy to determine the waiting position of an idle Automated Guided Vehicle(AGV) is proposed and its performance is compared with the existing waiting position policies. Unlike the existing policies, the queue length in the input buffer is considered in the new policy. As a result, the waiting position based on the new policy depends on the status of the system. The simulation result indicates that the proposed policy reduces the waiting time in both the input and the output buffers significantly, regardless of the number of AGVs in the system. Therefore, the manufacturing lead time can be minimized.

• Convergence Security Journal
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• v.5 no.1
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• pp.45-52
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• 2005

In this paper, the development specification of the optical burst switching system (OBS) for next generation internet services is presented. The development specification includes the number of input/output nodes, the number of wavelengths, buffer capacity, the capacity/queue size of the controller and maximum burst assembly delay. From the performance parameters related to the OBS design, an mathematical model to maximize the throughput and minimize the data loss is presented, and then efficient heuristic algorithm is also presented to analyze the sensitivity of the system parameters.

• Journal of electromagnetic engineering and science
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• v.6 no.1
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• pp.18-23
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• 2006

In this paper, we demonstrate a fully integrated X-band image rejection down converter, which was developed using InGaP/GaAs HBT MMIC technology, consists of two single-balanced mixers, a differential buffer amplifier, a differential YCO, an LO quadratue generator, a three-stage polyphase filter, and a differential intermediate frequency(IF) amplifier. The X-band image rejection downconverter yields an image rejection ratio of over 25 dB, a conversion gain of over 2.5 dB, and an output-referred 1-dB compression power$(P_{1dB,OUT})$ of - 10 dBm. This downconverter achieves broadband image rejection characteristics over a frequency range of 1.1 GHz with a current consumption of 60 mA from a 3-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.291-297
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 128-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array. This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We designed the circuits with goals of the high-speed computations and the simplified structures.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.61-63
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• 1987

In this paper, we develope a system which can perform signal processing for bar-code laser scanner. This system is composed of optical detector and preprocessor. The former detects the diffused light and converts it into TTL lebel output. The latter discriminator valid data from various raw data and transmits data to micro-processor. The preprocessor consists of edge transition detector, latch signal generator, module counter, register array, adder array, and buffer memory control circuit etc..

• The Transactions of the Korea Information Processing Society
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• v.6 no.3
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• pp.742-749
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• 1999

This paper proposes the mechanism of cell buffering in the output buffer of ATM switch for the traffic with the different QOS in the ATM environment. The proposed mechanism, VQS(Variable Queue Sharing) can minimize the cell loss ratio(CLR) of bursty traffic through the sharing of CBR queue, VBR queue, ABR queue to maximize the utilization of queue resource. To evaluate VQS performance, we make simulator using Visual Slam 2.0. We compare the CLP and cell average delay of VQS and HOL, QLT_HOL using the bursty traffic patterns.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.453-455
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• 1993

In this research, the digital signal processing PC board which employs TI's TMS320C25 is implemented. The board can perform following functions. spectrum analysis of speech and repetitive signal, digital filters emulation by convolution, signal generation of sinusoidal wave, rectangular wave etc.. In this system, communications between PC and DSP board. program down-loading to DSP board and recording and graphic of acquired and processed data in DSP board are executed by PC. Parallel interface and buffer memory are used in communications. Data acquisition and operation are carried out in DSP board. Resultant data are transmitted to PC and output through DAC.