• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.08a
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• pp.31-34
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• 2003

($Ba_{0.6-x}Sr_{0.4}Ca_x)TiO_3$ (BSCT) (x=0.10, 0.15, 0.20) powder, prepared by the sol-gel method, were mixed with organic vehicle and the BSCT thick films were fabricated by the screen-printing techniques on alumina substrates using the BSCT paste. The structural and the electrical properties were investigated for various composition ratio and sintering temperature. BSCT thick film thickness, obtained by four printings, was approximately 110 ~ 120 ${\mu}m$. The Curie temperature and dielectric constant at room temperature were decreased with increasing Ca content. The relative dielectric constant, dielectric loss and tunability of the BSCT(50/40/10) specimen, which was sintered at $1420^{\circ}C$ and measured at 1MHz, were about 910, 0.46% and 9.28% at 5kV/cm, respectively.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• 전자공학회논문지 IE
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• v.43 no.1
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• pp.1-4
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• 2006

The characteristics of polymeric thin-film transistors(TFTs) can be controlled by chemically modifying the surface of the gate dielectric prior to the organic semiconductor. The chemical treatment consists of derivative the tantalum pentoxide($Ta_2O_5$) surface with organic materials to form self-assembled monolayer(SAM). The deposition of an octadecyl-trichlorosilane(OTS), hexamethy-ldisilazone(HMDS), aminopropyltreithoxysilane(ATS) SAM leads to a mobility of $0.01\sim0.06cm2/V{\cdot}s$ in a poly-3-hexylthiophene(P3HT) conjugated polymer. The mobility enhancement mechanism is likely to involve molecular interactions between the polymer and SAM. These result can be used for polymer TFT's dielectric material.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.1
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• pp.12-16
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• 2011

In this study, we fabricated the flexible pentacene TFTs with the polymer gate dielectric and contact printing method by using the silver nano particle ink as a source/drain material on plastic substrate. In this experiment, to lower the cross-linking temperature of the PVP gate dielectric, UV-Ozone treatment has been used and the process temperature is lowered to $90^{\circ}C$ and the surface is optimized by various treatment to improve device characteristics. We tried various surface treatments; $O_2$ Plasma, hexamethyl-disilazane (HMDS) and octadecyltrichlorosilane (OTS) treatment methods of gate dielectric/semiconductor interface, which reduces trap states such as -OH group and grain boundary in order to improve the OTFTs properties. The optimized OTFT shows the device performance with field effect mobility, on/off current ratio, and the sub-threshold slope were extracted as $0.63cm^2 V^{-1}s^{-1}$, $1.7{\times}10^{-6}$, and of 0.75 V/decade, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.71-71
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• 2012

As the critical dimensions of integrated circuits are scaled down, the line width and spacing between the metal interconnects are made smaller. The dielectric film used as insulation between the metal lines contributes to the resistance-capacitance (RC) time constant that governs the device speed. If the RC time delay, cross talk and lowering the power dissipation are to be reduced, the intermetal dielectric (IMD) films should have a low dielectric constant. The introduction of Cu and low-k dielectrics has incrementally improved the situation as compared to the conventional $Al/SiO_2$ technology by reducing both the resistivity and the capacitance between interconnects. Some of the potential candidate materials to be used as an ILD are organic and inorganic precursors such as hydrogensilsequioxane (HSQ), silsesquioxane (SSQ), methylsilsisequioxane (MSQ) and carbon doped silicon oxide (SiOCH), It has been shown that organic functional groups can dramatically decrease dielectric constant by increasing the free volume of films. Recently, various inorganic precursors have been used to prepare the SiOCH films. The k value of the material depends on the number of $CH_3$ groups built into the structure since they lower both polarity and density of the material by steric hindrance, which the replacement of Si-O bonds with Si-$CH_3$ (methyl group) bonds causes bulk porosity due to the formation of nano-sized voids within the silicon oxide matrix. In this talk, we will be introduce some properties of SiOC(-H) thin films deposited with the dimethyldimethoxysilane (DMDMS: $C_4H_{12}O_2Si$) and oxygen as precursors by using plasma-enhanced chemical vapor deposition with and without ultraviolet (UV) irradiation.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.257-257
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• 2010

One of the critical issues for applications of flexible organic thin film transistors (OTFTs) for flexible electronic systems is the electrical stabilities of the OTFT devices, including variation of the current on/off ratio ($I_{on}/I_{off}$), leakage current, threshold voltage, and hysteresis, under repetitive mechanical deformation. In particular, repetitive mechanical deformation accelerates the degradation of device performance at the ambient environment. In this work, electrical stabilities of the pentacene organic thin film transistors (OTFTs) employing multi-stack hybrid encapsulation layers were investigated under mechanical cyclic bending. Flexible bottom-gated pentacene-based OTFTs fabricated on flexible polyimide substrate with poly-4-vinyl phenol (PVP) dielectric as a gate dielectric were encapsulated by the plasma-deposited organic layer and atomic layer deposited inorganic layer. For cyclic bending experiment of flexible OTFTs, the devices were cyclically bent up to $10^5$ times with 5mm bending radius. In the most of the devices after $10^5$ times of bending cycles, the off-current of the OTFT with no encapsulation layers was quickly increased due to increases in the conductivity of the pentacene caused by doping effects from $O_2$ and $H_2O$ in the atmosphere, which leads to decrease in the $I_{on}/I_{off}$ and increase in the hysteresis. With encapsulation layers, however, the electrical stabilities of the OTFTs were improved significantly. In particular, the OTFTs with multi-stack hybrid encapsulation layer showed the best electrical stabilities up to the bending cycles of $10^5$ times compared to the devices with single organic encapsulation layer. Changes in electrical properties of cyclically bent OTFTs with encapsulation layers will be discussed in detail.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.184-187
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• 2002

In this work, the electrical characteristics of organic thin film transistors with the stacked organic gate insulators have been studied. PVP(Polyvinylphenol) and polystyrene were used as gate insulating materials. Both the high dielectric constant of PVP and better insulating capability of polystyrene were compensatorily adopted in two different stacking orders of PVP-polystyrene and polystyrene-PVP. The output characteristics of the device with the stacked gate insulator showed substantial improvement compared with those of the devices with either PVP or polystyrene gate insulator: Furthermore, these stacked organic gate insulators can differently affect the TFT characteristics with the stacking orders. The electrical properties of TFTs with organic gate insulators stacked in different orders are discussed.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.661-664
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• 2004

In this paper, it was demonstrated that the organic thin film transistors with the organic gate insulators were fabricated by vapor deposition polymerization (VDP) processing. The configuration of OTFTs was a staggered-inverted top-contact structure and gate dielectric layer was deposited with 0.45 ${\mu}m$ thickness. In order to form polyimide as a gate insulator, VDP process was also introduced instead of spin-coating process. Polyimide film was respectively co-deposited with different materials. One was from a 4,4'-oxydiphthalic anhydride (ODPA) and 4, 4'-oxydianiline (ODA) and the other was from 2,2-bis(3,4-dicarboxyphenyl) hexafluoropropane dianhydride (6FDA) and ODA. And it was also cured at 150 $^{\circ}C$ for 1 hour followed by 200 $^{\circ}C$ for 1 hour. Electrical characteristics of the organic thin-film transistors were detailed comparisons between the ODPA-ODA and the 6FDA-ODA which were used as gate insulator.

• 전기의세계
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• v.16 no.4
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• pp.11-16
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• 1967

A physical analysis is applied to the measured phenomena of aromatic organic compounds under the uniform electric field of 0.1MV/cm through 1.5MV/cm, when they are irradiated or non-irradiated respectively. Upon the observations about irradiation effects, space charge effects and their temperature dependance, the conditions of lattice defects act conspicuously on electric conductrivity, photo conductivity and dielectric breakdown. Although the qualitative agreement with Frohlich's high energy criterion theory for the above mechanisms is poor, it is concluded that the phenomena of aromatic compounds may possibly be due to the effect of lattice defects or impurity centers generated by .gamma.-ray irradiations.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.287-287
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• 2008