• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• The Korean Journal of Archival Studies
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• no.18
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• pp.139-178
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• 2008

The functional requirements standards for electronic records management systems which have been published recently describe the specifications very precisely including not only core functions of records management but also the function of system management and optional modules. The fact that these functional requirements standards seem to be similar to each other in terms of the content of functions described in the standards is linked to the global standardization trends in the practical area of electronic records. In addition, these functional requirements standards which have been built upon with collaboration of archivists from many national archives, IT specialists, consultants and records management applications vendors result in not only obtaining high quality but also establishing the condition that the standards could be the certificate criteria easily. Though there might be a lot of different ways and approaches to benchmark the functional requirements standards developed from advanced electronic records management practice, this paper is showing the possibility and meaningful business cases of gaining useful practical ideas learned from imaging electronic records management practices related to the functional requirements standards. The business cases are explored central functions of records management and the intellectual control of the records such as classification scheme or disposal schedules. The first example is related to the classification scheme. Should the records classification be fixed at same number of level? Should a record item be filed only at the last node of classification scheme? The second example addresses a precise disposition schedule which is able to impose the event-driven chronological retention period to records and which could be operated using a inheritance concept between the parent nodes and child nodes in classification scheme. The third example shows the usage of the function which holds or freeze and release the records required to keep as evidence to comply with compliance like e-Discovery or the risk management of organizations under the premise that the records management should be the basis for the legal compliance. The last case shows some cases for bulk batch operation required if the records manager can use the ERMS as their useful tool. It is needed that the records managers are able to understand and interpret the specifications of functional requirements standards for ERMS in the practical view point, and to review the standards and extract required specifications for upgrading their own ERMS. The National Archives of Korea should provide various stakeholders with a sound basis for them to implement effective and efficient electronic records management practices through expanding the usage scope of the functional requirements standard for ERMS and making the common understanding about its implications.