• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.7
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• pp.583-590
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• 2002

In this paper, a new Silicon on Insulator (SOI)-based photodetector was proposed, and its basic operation principle was explained. Fabrication steps of the detector are compatible with those of conventional SOI CMOS technology. With the proposed structure, RGB (Read, Green, Blue) which are three primary colors of light can be realized without using any organic color filters. It was shown that the characteristics of the SOI-based detector are better than those of bulk-based detector. To see the response characteristics to the green (G) among RGB, SOI and bulk NMOSFETS were fabricated using $1.5\mu m$ CMOS technology and characterized. We obtained optimum optical response characteristics at $V_{GS}=0.35 V$ in NMOSFET with threshold voltage of 0.72 V. Drain bias should be less than about 1.5 V to avoid any problem from floating body effect, since the body of the SOI NMOSFET was floated. The SOI and the bulk NMOSFETS shown maximum drain currents at the wavelengths of incident light around 550 nm and 750 nm, respectively. Therefore the SOI detector is more suitable for the G color detector.

• Proceedings of the KIEE Conference
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• 2004.05a
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• pp.92-94
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• 2004

We become an industry information society which is advanced to the altitude with the today. The information to be loading various goods each other together at a circumstance environment is increasing extremely. The restriction recognizes the data of many Quantity and it follows because the human deals the task to classify. The development of a mathematical formulation for solving a problem like this is often very difficult. But Artificial intelligent systems such as neural networks have been successfully applied to solving complex problems in the area of pattern recognition and classification. So, in this paper a neural network approach is used to recognize and classification problem was broken into two steps. The first step consist of using a neural network to recognize the existence of purpose pattern. The second step consist of a neural network to classify the kind of the first step pattern. The neural network leaning algorithm is to use error back-propagation algorithm and to find the weight and the bias of optimum. Finally two step simulation are presented showing the efficacy of using neural networks for purpose recognition and classification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.11
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• pp.2479-2485
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• 2013

In this paper, we present a design for solid-state radar SSPA with sequential bias. We apply to variable extension pulse generator to eliminate signal distortion which is caused by bias rising/falling delay of power amplifier. There is an optimum impedance matching circuit to have high efficiency of GaN-power device by measuring microwave characteristics through load-pull method. The designed SSPA is consisted of pre-amplifier, drive-amplifier and main-amplifier as a three stages to apply for X-Band solid-state radar. Thereby we made a 200W SSPA which has output pulse maximum power shows 53.67dBm and its average power is 52.85dBm. The optimum design of transceiver module for solid-state pulse compression radar which is presented in this dissertation, it can be available to miniaturize and to improve the radar performances through additional research for digital radar from now on.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.261-264
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• 2005

This paper presents the design of a down-conversion mixer with built-in active balun integrated in a $0.25\;{\mu}m$ pHEMT process. The active balun consists of series-connected common-gate FET and common-source FET. The designed balun achieved broadband characteristics by optimizing gate-width and bias condition for the reduction in parasitic effect. From DC to more than 6GHz, the active balun shows the phase error of less than 3 degree and the gain error of less than 0.4 dB. A single-balanced down-conversion mixer with built-in broadband active balun has been designed with optimum width, load resistor and bias for conversion gain and without any matching component for broadband operating. The designed mixer whose size of including on-chip bias circuit is $1\;mm{\times}1\;mm$ shows the conversion gain of better than 7 dB from 2 GHz to 6 GHz and $P_{1dB}$ of -10 dBm at 5.8 GHz

• Journal of the Korean Vacuum Society
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• v.8 no.4B
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• pp.541-547
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• 1999

Reactive ion etching process for InP using BCl3/O2/Ar high density inductively coupled plasma was investigated. The experimental design method proposed by the Taguchi was utilized to cover the whole parameter range while maintaining reasonable number of actual experiments. Results showed that the ICP power and the chamber pressure were the two dominant parameters affectsing etch results. It was also observed that the etch rate decreased and the surface roughness improved as the ICP power and the bias voltage increased and as the chamber pressure decreased. The Addition of oxygen to the gas mixture drastically improved surface roughness by suppressing the formation of the surface reaction product. The optimum condition was ICP power 600W, bias voltage -100V, 10% $O_2$, 6mTorr, and $180^{\circ}C$, resulting in about 0.15$\mu\textrm{m}$ etch rate with smooth surfaces and vertical mesa sidewalls Also, the maximum etch rate of abut 4.5 $\mu\textrm{m}$/min was obtained at the condition of ICP power 800W, bias voltage -150V, 15% $O_2$, 8mTorr and $160^{\circ}C$.

• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.21-24
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• 2005

The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been very important issue. So in this experiment, we calculated error rate of RSFQ switch in superconductiyity ALU, The RSFQ switch should have a very low error rate in the optimal bias. We prepared two circuits Placed in parallel. One was a 10 Josephson transmission lines (JTLs) connected in series, and the other was the same circuit but with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to the both circuits. The outputs of the two circuits were compared with an RSFQ XOR to measure the error rate of the RSFQ switch. By using a computerized bit error rate test setup, we measured the bit error rate of 2.18$\times$$10^{12}$ when the bias to the RSFQ switch was 0.398mh that was quite off from the optimum bias of 0.6mA.

• Progress in Superconductivity
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• v.7 no.1
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• pp.36-40
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• 2005

The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been a very important issue. In this work, we calculated the bit error rate of an RSFQ switch used in superconductive arithmetic logic unit (ALU). RSFQ switch should have a very low error rate in the optimal bias. Theoretical estimates of the RSFQ error rate are on the order of $10^{-50}$ per bit operation. In this experiment, we prepared two identical circuits placed in parallel. Each circuit was composed of 10 Josephson transmission lines (JTLs) connected in series with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to both circuits. The outputs of the two circuits were compared with an RSFQ exclusive OR (XOR) to measure the bit error rate of the RSFQ switch. By using a computerized bit-error-rate test setup, we measured the bit error rate of $2.18{\times}10^{-12}$ when the bias to the RSFQ switch was 0.398 mA that was quite off from the optimum bias of 0.6 mA.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.4
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• pp.367-372
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• 2002

The vertically well-aligned carbon nanotubes(CNTs) were successfully grown on Ni coated silicon wafer substrate by DC bias-assisted PECVD(Plasma Enhanced Chemical Vapor Deposition). As a catalyst, Ni thin film of thickness ranging from 15~30nm was prepared by electron beam evaporator method. In order to find the optimum growth condition, the type of gas mixture such as $C_2H_2-NH_3$ was systematically investigated by adjusting the gas mixing ratio at $570^{\circ}C$ under 0.4Torr. The diameter of the grown CNTs was 40~200nm and the diameter of the CNTs increased with increasing the Ni particles size. TEM images clearly showed carbon nanotubes to be multiwalled. The measured turn-on field was $3.9V/\mu\textrm{m}$ and an emission current of $1.4{\times}10^4A/\textrm{cm}^2$ was $7V/\mu\textrm{m}$. The CNTs grown by bias-assisted PECVD was able to demonstrate high quality in terms of vertical alignment, crystallization of graphite and the processing technique at low temperature of $570^{\circ}C$ and this can be applied for the emitter tip of FEDs.

• Journal of Advanced Marine Engineering and Technology
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• v.9 no.3
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• pp.250-256
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• 1985

With the advant of thryistors having large peak inverse voltages, current-source inverters are becoming very popular to feed induction motors. But it is very difficult to analysis the commutation. Since the actual variation of current during commutation is neither instantaneous nor linear and is effected by many parameters. Minimized bias-time of reverse voltages during commutation is expressed in term of machine parameters, capacitor voltage, load current and so on. The minimized bias-time is computed with y and z and also the commuation mechanism is tested on 2.2 kw induction motor. The computed results are compared with the experimental results, and the results give a good information for designing the commutation mechanism.

• Transactions on Electrical and Electronic Materials
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• v.12 no.2
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• pp.43-50
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• 2011

Carbon-nanotube metal oxide semiconductor field effect transistor (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16 nm N-type CN-MOSFETs are explored in this paper. The optimum N-type CN-MOSFET device profiles with different number of tubes are identified for achieving the highest on-state to off-state current ratio ($I_{on}/I_{off}$). The influence of substrate voltage on device performance is also investigated in this paper. Tradeoffs between subthreshold leakage current and overall switch quality are evaluated with different substrate bias voltages. Technology development guidelines for achieving high-speed, low-leakage, area efficient, and manufacturable carbon nanotube integrated circuits are provided.