• 대한전자공학회논문지SD
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• 제49권8호
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• pp.22-26
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• 2012

본 논문에서는 0.18um CMOS(1P4M) 공정을 이용하여 HDMI용 액티브 광케이블에 적합한 채널당 2.5-Gb/s의 동작 속도를 갖는 광 수신기를 구현하였다. 광 수신기는 차동 증폭구조를 가지는 트랜스임피던스 증폭기, 5개의 증폭단을 갖는 리미팅 증폭기, 출력 버퍼단으로 구성된다. 트랜스임피던스 증폭기는 피드백 저항을 가진 인버터 입력구조로 구현함으로써 낮은 잡음지수와 작은 전력소모를 갖도록 설계하였다. 연이은 차동구조 증폭기 및 출력 버퍼단을 통해 전체 전압이득을 증가하였고, 리미팅 증폭단과의 연동을 용이하게 했다. 리미팅 증폭기는 다섯 단의 증폭단과 출력 버퍼단, 옵셋 제거 회로단으로 이루어져 있다. 시뮬레이션 결과, 제안한 광 수신기는 $91dB{\Omega}$ 트랜스임피던스 이득, 1.55 GHz 대역폭(입력단 0.32 pF의 포토다이오드 커패시턴스 포함), 16 pA/sqrt(Hz) 평균 잡음 전류 스펙트럼 밀도, 및 -21.6 dBm 민감도 ($10^{-12}$ BER)를 갖는다. 또한, DC 시뮬레이션 결과, 1.8-V의 전원전압에서 총 40 mW의 전력을 소모한다. 제작한 칩은 패드를 포함하여 $1.35{\times}2.46mm^2$의 면적을 갖는다. optical eye-diagram 측정 결과, 2.5-Gb/s 동작속도에서 크고 깨끗한 eye-diagram을 보인다.

• 한국광학회:학술대회논문집
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• 한국광학회 2004년도 하계학술발표회
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• pp.16-17
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• 2004

• 전자공학회논문지SC
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• 제37권6호
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• pp.25-34
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• 2000

본 논문에서 범용의 CMOS 트랜지스터 공정을 사용하여 250-Mbps 10-채널 CMOS 광 수신기 어레이칩을 설계하였다. 이러한 광 수신기 어레이는 병렬 광 신호 전송 시스템의 성능을 결정하는 가장 중요한 블록이며 이를 CMOS 트랜지스터로 설계함으로써 낮은 단가의 시스템의 구현을 가능하게 하였다. 각 데이터 채널은 집적화 된 광 검출 소자 및 여러 단의 증폭기로 구성된 아날로그 프런트-엔드, D-FF (D-flip flop)과 칩 외부 구동기로 구성된 디지털 블록으로 구성되어 있다. 전체 칩은 광 수신기 어레이와 데이터의 동기식 복원을 위해 PLL (Phase-Lock Loop) 회로로 구성 되어있다. 설계한 광 수신기 어레이 칩은 0.65-㎛ 2-poly, 2-metal CMOS 공정을 사용하여 제작하였으며, 각 채널은 ±2.5V의 전원 전압에 대하여 330㎽의 소비 전력을 보였다.

• 한국광학회지
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• 제5권2호
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• pp.333-339
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• 1994

단일모드 광섬유를 부착한 고속 광통신용 PIN-전치증폭기 모듈을 GaInAs PIN 광검출기와 GaAs 전치증폭기를 하이브리드로 집적하여 제작하였다. PIN 광검출기의 정전용량은 0.35pF이었으며 이 소자의 수광직경은 $20{\mu}m$였다. 제작된 수광모듈의 -3dB 차단주파수는 2GHz 이상이었으며 2.5Gbps NRZ$(PRBS=2^{23}-1)$ 입력광신호에 대해 비트오율이 $10^{-9}$일 때 -25.2dBm의 수신감도를 보였다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.136-139
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• 2003

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of signal amplifiers, a nonlinear circuit with diodes, and a bandpass filter Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s NRZ signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• ETRI Journal
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• 제35권2호
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• pp.245-252
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• 2013

In this work, we study the physical layer solutions for 10-gigabit-capable passive optical networks (PONs), particularly for an optical link terminal (OLT) including a 10-Gbit/s electroabsorption modulated laser (EML) and a 2.5-Gbit/s burst mode receiver (BM-Rx) in a novel bidirectional optical subassembly (BOSA). As unique features, a bidirectional mini-flat package and a 9-pin TO package are developed for a 10-gigabit-capable PON OLT BOSA composed of a 1,577-nm EML and a 1,270-nm avalanche photodiode BM-Rx, including a single-chip burst mode integrated circuit that is integrated with a transimpedance and limiting amplifier. In the developed prototype, the 10-Gbit/s transmitter and 2.5-Gbit/s receiver characteristics are evaluated and compared with the physical media dependent (PMD) specifications in ITU-T G.987.2 for XG-PON1. By conducting the 10-Gbit/s downstream and 2.5-Gbit/s upstream transmission experiments, we verify that the developed 10-gigabitcapable PON PMD prototype can operate for extended network coverage of up to a 40-km fiber reach.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.487-489
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• 2005

This paper proposes a symbol timing recovery method that is simple in structure and can provide high speed symbol synchronization. Transmitter and receiver are not synchronized in communication systems using digital modulation. Receiver should search the timing variation of transmitter continuously. The proposed timing recovery method searches sample position by comparing previous sample value with next sample value. This method can be applied to digital and optical transceivers with high data rate.

• 전자공학회논문지A
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• 제33A권11호
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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• pp.229-231
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• 2000

Nowadays, the telecommunication service provider has witnessed an unprecedented growth in data traffic and the need for networking. optical fiber can provide some THz of huge bandwidth WDM technology has been an emerging issue for the efficient use of optical links. WDM uses a number of different wavelength that are assigned to each channel. The minimal number of optical transceivers and receivers should be used in a node to build an economic WDM transmission system without degrading system performance. Hence, the analysis of performance parameters such as throughput and delay is important to guarantee the WDM system performance. in this paper, the performance of a MAC protocol on a slotted WDM system that has a tunable transmitter(Txt), a tunable receiver(Rxt), and a fixed receiver(Rxf), respectively, on each node, was statistically analyzed The computer simulation validates the performance analysis.

• Journal of the Optical Society of Korea
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• 제6권3호
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• pp.105-107
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• 2002

We propose 'variable decision threshold technique' to decrease the power penalty induced by low-frequency tones. The proposed scheme uses a simple low-speed receiver to change the decision threshold of the optical receiver according to the low-frequency tones. We demonstrate the proposed method at 2.5 Gb/s.