• Journal of Wind Energy
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• v.14 no.4
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• pp.50-56
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• 2023

With the abnormal weather phenomena caused by global warming, the frequency and intensity of lightning strikes are increasing, and lightning accidents are becoming one of the biggest causes of failures and accidents in offshore wind turbines. In order to secure generator operation reliability, effective and practical measures are needed to reduce lightning damage. Because offshore wind turbines are tall structures installed at sea, the possibility of direct lightning strikes is very high compared to other structures, and the role of surge protection devices to minimize damage to the electrical and electronic circuits inside the wind turbine is very important. In this study, a varistor, which is a key element for a class 1 surge protection device for direct lightning protection, was developed. The current density was improved by changing the varistor composition, and the distance between the electrode located on the varistor surface and the edge of the varistor was optimized through a simulation program to improve the fabrication process. Considering the combined effects of heat distribution, electric field distribution, and current density on the optimized varistor surface, silver electrodes were formed with a gap of 0.5 mm. The varistor developed in this study was confirmed to have an energy tolerance of 10/350 ㎲, 50kA, which is a representative direct lightning current waveform, and good protection characteristics with a limiting voltage of 2 kV or less.

• Journal of Korean Society of Environmental Engineers
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• v.31 no.4
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• pp.249-255
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• 2009

The performance of microbial fuel cell (MFC) can be affected by many factors including the rate of organic matter oxidation, the electron transfer to electrode by electrochemical bacteria, proton diffusion, the concentration of electron acceptor, the rate of electron acceptor reduction and internal resistance. the performance of MFC using oxygen as electron acceptor can be influenced by oxygen concentration as limit factors in cathode compartment. Many studies have been performed to enhance electricity production from MFC. The series or parallel stacked MFC connected several MFC units can use to increase voltages and currents produced from MFCs. In this study, a single MFC (S-MFC) and a stacked MFC (ST-MFC) using acetate as electron donor and oxygen as electron acceptor were used to investigate the influence of dissolved oxygen (DO) concentrations in cathode compartment on MFC performance. The power density (W/$m^3$) of S-MFC was in order DO 5 > 3 > 7 > 9 mg/L, the maximum power density (W/$m^3$) of S-MFC was 42 W/$m^3$ at DO 5 mg/L. The power density (W/$m^3$) of ST-MFC was in order DO 5 > 7 > 9 > 3 mg/L and the maximum power density (W/$m^3$) of STMFC was 20 W/$m^3$ at DO 5 mg/L. These results suggest that the DO concentration of cathode chamber should be considered as important limit factor of MFC operation and design for stacked MFC as well as single MFC. The results of ST-MFC operation showed the voltage decrease of some MFC units by salt formation on the surface of anode, resulting in decrease total voltage of ST-MFC. Therefore, connecting MFC units in parallel might be more appropriate way than series connections to enhance power production of stacked MFC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Korean Journal of Materials Research
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• v.3 no.6
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• pp.632-637
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• 1993

The optical properties and electrochromism of amorphous $WO_3$ thin films were studied. $WO_3$ thin films with thickness of 3000$\AA$~6000$\AA$ were deposited by vacuum evaporat.ion. All these films were transparent and found to be amorphous in structure by X-ray diffraction analysis and the visible wave length refractive indices were found to be between 1.9 and 2.1 and the optical energey gap to be 3.25 eV. Electrochromic devices were made consisting of IT0 transparent electrode, $WO_3$ thin films, $LiCIO_4$- propylene carbonate and Pt counter electrode. In terms of their operation, the amorphous $WO_3$ films were colored blue by a double injection of electrons from the transparent electrode and lithium ions from the $LiCIO_4$-propylene carbonate organic electrolyte and made colorless by electrochemical oxidation reaction. The electrochromic properties of $WO_3$ thin films including coloration and bleaching, optical density and response time were all found to be strongly dependent on the film deposition condition, electrolyte concentration, sheet resistance of the transparent electrode and applied voltage.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.2343-2348
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• 2014

Main ground net of power plant is formed to protect human body from increase in potential gradient caused by grounding current during ground fault. Calculations during ground design are generally performed according to IEEE Std-80-2000 (Kepco Design Standard 2602). However, it is difficult to apply this Standard to water environment, and a grounding technology is required to secure grounding resistance of floating photovoltaic system. Therefore the aim of this paper is to investigate and analyze ground resistivity on the water surface and underwater of reservoir using Wenner 4-pin method, a general method of measuring ground resistivity. Also, grounding resistance of floating photovoltaic systems currently in operation was measured and analyzed using the voltage drop method suggested in the international standard (IEEE Std-81) to propose a grounding method for stable grounding of floating photovoltaic system. The resistivity at 1m below the surface of water ($126.3969[{\Omega}{\cdot}m]$) is mostly higher than resistivity at the river bed ($97.5713[{\Omega}{\cdot}m]$). Also the proposed grounding anchor method was determined as the most effective method of securing stable grounding resistance in floating photovoltaic systems and is expected to be utilized as a ground method for future floating photovoltaic generation systems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• Journal of Soil and Groundwater Environment
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• v.10 no.5
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• pp.11-17
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• 2005

Characteristics of phenanthrene removal in the Electrokinetic (EK)-Fenton process were investigated in a 2-dimensional test cell in a viewpoint of the effect of gravity and electrosmotic flow (EOF). When the constant voltage of 100 V was applied to this system, the current decreased from 1,000 to 290 mA after 28 days, because soil resistance increased due to the exhaustion of ions in soil by electroosmosis and electromigration. Accumulated EOF in two cathode reservoirs was 10.3 L and the EOF rate was kept constant for 28 days. At the end of operation, the concentration of phenanthrene was observed to be very low near the anode and increased in the cathode region because hydrogen peroxide was supplied from anode to cathode region following the direction of EOP. Additionally, the concentration of phenanthrene decreased at the bottom of the test cell because the electrolyte solution containing hydrogen peroxide was largely transported toward the bottom due to a low capillary action in the soil with high porosity. Average removal efficiency of phenanthrene by EK-Fenton process was 81.4% for 28 days. In-situ EK-Fenton process would overcome the limitations of conventional remediation technologies and effectively remediate the contaminated sites.

• KEPCO Journal on Electric Power and Energy
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• v.2 no.4
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• pp.577-582
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• 2016

This Study focused on the development of SMPS (Switching Mode Power Supply) to supply the constant votage and current nevertheless LED fluorescent Light generated the electric noise (with Harmonics) and Inrush current at instant time of turn-on and off. Recently, according to the Green policy in government, the LED fluorescent Lighter showed the rapidly increasing tend as indoor and outdoor Lighter. But, because of costs, LED fluorescent Light not considered and neglected the following items; power factor, efficiency, Harmonics and Inrush current. So, we are developed the SMPS about 3 key issues as follows: 1st, power factor and efficiency is 85%. 2nd, the switching noisy by harmonic is minimized. 3rd, the Inrush current at turn on and off time is reduced the minimum 0.3 A after $100{\mu}sec$ on turnon time. The proposed SMPS adjusted by LNK 409 driver (included the high frequency modulation function). Although, the developed SMPS maintained the about 85% of power factor and efficiency. but, the SMPS must be generated low heat by the variation of minute load current at switching timing. To improve the above weak point, the developed SMPS have the feedback monitoring circuit between input side and output side to maintain the power factor and efficiency. Also, we are studied the time-constant of control circuit to output the constant voltage and current nevertheless the load disturbance of LED lighting. The LED fluorescent Light of 46W is checked the above items.