• Title/Summary/Keyword: Operation mode

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Rotordynamic Analysis of a Dual-Spool Turbofan Engine with Focus on Blade Defect Events (블레이드 손상에 따른 이축식 터보팬 엔진의 동적 안정성 해석)

  • Kim, Sitae;Jung, Kihyun;Lee, Junho;Park, Kihyun;Yang, Kwangjin
    • Tribology and Lubricants
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    • v.36 no.2
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    • pp.105-115
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    • 2020
  • This paper presents a numerical study on the rotordynamic analysis of a dual-spool turbofan engine in the context of blade defect events. The blades of an axial-type aeroengine are typically well aligned during the compressor and turbine stages. However, they are sometimes exposed to damage, partially or entirely, for several operational reasons, such as cracks due to foreign objects, burns from the combustion gas, and corrosion due to oxygen in the air. Herein, we designed a dual-spool rotor using the commercial 3D modeling software CATIA to simulate blade defects in the turbofan engine. We utilized the rotordynamic parameters to create two finite element Euler-Bernoulli beam models connected by means of an inter-rotor bearing. We then applied the unbalanced forces induced by the mass eccentricities of the blades to the following selected scenarios: 1) fully balanced, 2) crack in the low-pressure compressor (LPC) and high pressure compressor (HPC), 3) burn on the high-pressure turbine (HPT) and low pressure compressor, 4) corrosion of the LPC, and 5) corrosion of the HPC. Additionally, we obtained the transient and steady-state responses of the overall rotor nodes using the Runge-Kutta numerical integration method, and employed model reduction techniques such as component mode synthesis to enhance the computational efficiency of the process. The simulation results indicate that the high-vibration status of the rotor commences beyond 10,000 rpm, which is identified as the first critical speed of the lower speed rotor. Moreover, we monitored the unbalanced stages near the inter-rotor bearing, which prominently influences the overall rotordynamic status, and the corrosion of the HPC to prevent further instability. The high-speed range operation (>13,000 rpm) coupled with HPC/HPT blade defects possibly presents a rotor-case contact problem that can lead to catastrophic failure.

Study of the Operation of Actuated signal control Based on Vehicle Queue Length estimated by Deep Learning (딥러닝으로 추정한 차량대기길이 기반의 감응신호 연구)

  • Lee, Yong-Ju;Sim, Min-Gyeong;Kim, Yong-Man;Lee, Sang-Su;Lee, Cheol-Gi
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.17 no.4
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    • pp.54-62
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    • 2018
  • As a part of realization of artificial intelligence signal(AI Signal), this study proposed an actuated signal algorithm based on vehicle queue length that estimates in real time by deep learning. In order to implement the algorithm, we built an API(COM Interface) to control the micro traffic simulator Vissim in the tensorflow that implements the deep learning model. In Vissim, when the link travel time and the traffic volume collected by signal cycle are transferred to the tensorflow, the vehicle queue length is estimated by the deep learning model. The signal time is calculated based on the vehicle queue length, and the simulation is performed by adjusting the signaling inside Vissim. The algorithm developed in this study is analyzed that the vehicle delay is reduced by about 5% compared to the current TOD mode. It is applied to only one intersection in the network and its effect is limited. Future study is proposed to expand the space such as corridor control or network control using this algorithm.

Development of 2-kW Class C Amplifier Using GaN High Electron Mobility Transistors for S-band Military Radars (S대역 군사 레이더용 2kW급 GaN HEMT 증폭기 개발)

  • Kim, Si-Ok;Choi, Gil-Wong;Yoo, Young-Geun;Lim, Byeong-Ok;Kim, Dong-Gil;Kim, Heung-Geun
    • The Journal of the Korea institute of electronic communication sciences
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    • v.15 no.3
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    • pp.421-432
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    • 2020
  • This paper proposes a 2-kW solid-state power amplifier (SSPA) developed by employing power amplifier pallets designed using gallium-nitride high electron mobility transistors, which is used in S-band military radars and to replace existing traveling-wave tube amplifier (TWTA). The SSPA consists of a high-power amplifier module, which combines eight power amplifier pallets, a drive amplifier module, a digital control module, and a power supply unit. First, the amplifier module and component were integrated into a small package to account for space limitations; next, an on-board harmonic filter was fabricated to reject spurious components; and finally, an auto gain control system was designed for various duty ratios because recent military radar systems are all active phase radars using the pulse operation mode. The developed SSPA exhibited a max gain of 48 dB and an output power ranging between 63-63.6 dBm at a frequency band of 3.1 to 3.5 GHz. The auto gain control function showed that the output power is regulated around 63 dBm despite the fluctuation of the input power from 15-20 dBm. Finally, reliability of the developed system was verified through a temperature environment test for nine hours at high (55 ℃) / low (-40℃) temperature profile in accordance with military standard 810. The developed SSPA show better performance such as light weight, high output, high gain, various safety function, low repair cost and short repair time than existing TWTA.

A Study on Automatic Interface Generation by Protocol Mapping (Protocol Mapping을 이용한 인터페이스 자동생성 기법 연구)

  • Lee Ser-Hoon;Kang Kyung-Goo;Hwang Sun-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.8A
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    • pp.820-829
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    • 2006
  • IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

On Designing Domino CMOS Circuits for High Testability (고 Testability를 위한 Domino CMOS회로의 설계)

  • 이재민;강성모
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.3
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    • pp.401-417
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    • 1994
  • In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

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A Study on the Anaerobic Treatment of the Phenol-bearing Wastewater with two Sludge Blanket-Packed Bed Reactors in Series (2단의 슬러지-고정상 반응기에서 페놀 함유 폐수의 혐시성 처리에 관한 연구)

  • 정종식;안재동;박동일;신승훈;장인용
    • Journal of Environmental Health Sciences
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    • v.21 no.4
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    • pp.1-9
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    • 1995
  • This study was carried to investigate the biodegradability of phenol in the wastewater with the two sludge blanket-packed bed reactor in series. Each reactor had a dimension of 0.09 m i.d. and 1.5 m height and consisted of two regions. The lower region was a sludge blanket of 0.5 m height and the upper region was a packed-bed of 1 m height. The packed bed region was charged with ceramic raschig rings of 10 mm i.d., 15 mm o.d. and 20 mm length. The reactors were operated at 35$\circ$C and the hydraulic retention time(HRT) was maintained 24 hours. The synthetic wastewater composed of glucose and phenol as major components was fed into the reactor in a continuous mode with incereasing phenol concentration. In addition, the nutrient trace metals($Na^+, Mg^{2+}, Ca^{2+}, PO_4^{3-}, NH_4^+, Co^{2+}, Fe^{2+}$ etc.) were added for growing anaerobes. The phenol concentration of the effluent, the overall gas production, the composition of product gas, the efficiency of COD reduction and the duration of acclimation period were measured to determine the performance of the anaerobic wastewater treatment system as the phenol concentration of the influent was increased from 600 to 2400 mg//l. Successfully stable biodegradation of phenol could be achieved with the anaerobic treatment system from 600 to 1, 800 mg/l of the influent phenol concentration. The upper level of influent phenol loading was high enough to meet most of the practical requirement. The duration of acclimation increased with the phenol loading. At steady state of the influent phenol concentration of 1800 mg/l, the treatment performance indicated the phenol reduction efficiency of 99%, the COD reduction efficiency of 99% and the gas production rate of 37 l/day. At the influent phenol concentration of 2400 mg/l, however, the operation of the treatment system was noted unstable. While the concentration of methane in biogas decreased with increasing the influent phenol loading, the carbon dioxide was increased. However, the concentration of hydrogen was varied negligibly. The concentration of methane was high enough to be used as a fuel. As a result, it is suggested that anaerobic phenol wastewater treament was economical in the sense of energy recovery and wastewater treatment.

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Structural Strength Evaluation for Development of a Vertical Transfer Device for a Personal Rapid Transit (PRT) Vehicle (PRT 차량용 수직이송장치의 개발을 위한 구조강도 평가)

  • Kang, Seok-Won;Um, Ju-Hwan;Jeong, Rag-Gyo;Song, Joon-Hyun
    • Transactions of the KSME C: Technology and Education
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    • v.3 no.3
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    • pp.165-173
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    • 2015
  • This paper presents numerical results of static structural stability analysis in development of a vertical transfer device of a PRT(Personal Rapid Transit) vehicle. The vertical transfer of a fully occupied vehicle operating on a road network is the first attempt, which is expected to contribute to overcome the limitations of conventional 2-dimensional operation mode. In particular, the vertical transfer apparatus designed based on vertical circulating conveyors is capable of continuous transfer without time delay so that it enables to accommodate a high traffic density. This system has been frequently used in a logistics field; however, it is essential to assess a structural integrity because an external force by a vehicle weight is exerted on the conveyors in the form of a concentrated load unlike a conventional logistic transport. In this study, prior to the production process, the structural performance of the pilot design in an early stage is numerically evaluated using the commercial finite element method (FEM) solver (i.e., $Ansys^{(R)}$).

Design of a Rectangular Waveguide Antenna for Automotive Side and Rear Radar Sensor Applications (차량 측후방 레이더 센서용 직사각형 도파관 안테나 설계)

  • Lee, Jae-Min;Ryu, Hong-Kyun;Woo, Jong-Myung;Koo, Bon-Hee
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.11 no.1
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    • pp.42-52
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    • 2012
  • In this paper, a waveguide antenna is designed and fabricated for side and rear radar sensor of vehicles in UWB (Ultra Wide Band) high band (center frequency : 9.5 GHz, -10 dB bandwidth : 600 MHz (6.4 %)). For the radar antenna, a probe fed rectangular waveguide antenna having simple structure and wide bandwidth is used. An important performance factor in this antenna is the isolation between transmitting (TX) and receiving (RX) waveguide antennas because this radar system uses TX and RX antennas separately. Thus the isolation between two antennas was simulated for E-plane and H-plane array. As a result, it was verified that the isolation of the H-plane array of the antennas is better than E-plane array, due to the TE10 mode. Therefore, H-plane arrayed waveguide antennas were mounted on a T-shaped radar module and performance of antennas was investigated. The -10 dB bandwidth of the TX and RX antenna mounted on T-shaped radar module was measured as 1000 MHz (10.52 %) and 1090 MHz (11.47 %) respectively and the isolation is less than -50 dB in the operation band. The peak gain is 7.65 dBi for the TX antenna and 7.26 dBi for the RX antenna and the beamwidth of H-plane of TX and RX antenna was measured as $64^{\circ}$ and $65^{\circ}$ respectively. Consequently, we verified that the proposed waveguide antenna is appropriate for a vehicle radar applications.

Design and Verification of Efficient On-Chip Debugger for Core-A (Core-A를 위한 효율적인 On-Chip Debugger 설계 및 검증)

  • Xu, Jingzhe;Park, Hyung-Bae;Jung, Seung-Pyo;Park, Ju-Sung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.4
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    • pp.50-61
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    • 2010
  • Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.

A Study on the Calculation of $CO_2$ Emission and Road Freight Environmental Index for Logistics Companies (물류기업의 온실가스 배출량 및 도로화물환경지표 산정에 관한 연구)

  • Kim, Jong-Hyeon;Kim, Hong-Sang;Choe, Sang-Jin;Park, Seong-Gyu;Kim, Jeong;Jang, Yeong-Gi
    • Journal of Korean Society of Transportation
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    • v.29 no.2
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    • pp.25-35
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    • 2011
  • In order to reduce Green House Gas(GHG) reduction in the road freight sector and thus establish green logistics, running efficiency of goods vehicles is of paramount importance. Providing effective transportation infrastructure can contribute to achieve the green logistics by reducing empty running of heavy goods vehicles and van, increasing the average payload on the vehicle, and shifting the transportation mode. In order to reduce the environmental impact from the road freight sector, it is essential to quantify the amount of environmental loading from the sector. However, any systematic survey on the environmental loading from the logistics companies has not been carried out in Korea. In this study, the environmental index for the road freight sector is defined as the amount of $CO_2$ emission per ton km generated from goods vehicles. The computational analysis shows that the average $CO_2$ emission per ton km generated by the logistics companies in Korea is $363g-CO_2/ton{\cdot}km$. Compared to UK (=$130g-CO_2/ton{\cdot}km$) and France (=$97g-CO_2/ton{\cdot}km$), the efficiency of logistics in Korea is 2.8 and 3.7 times as low as in the advanced countries. It also indicates that the main reasons for the low efficiency are mainly due to the high rate of empty operation of goods vehicles and the low payload.