• The Journal of the Acoustical Society of Korea
• /
• v.15 no.5
• /
• pp.13-20
• /
• 1996

Recently, for implementation of neural networks extensive studies have been done especially VLSI technology has been regarded as the one of the most attractive means to implement neural networks. The main drawbacks of digital VLSI implementations are their large area and slow processing speed. In this paper to solve the speed and size problems we designed the efficient architecture using the binary convolution method for basic operation of neural cell, multiplication and addition. When it is used for implementing 3-layer network with 16 neural cell per layer that used neural cell based on binary convolution, clock of 50MHz and 26MCPS on 0.8${\mu}$ standard cell library has been achieved.

• Journal of Institute of Control, Robotics and Systems
• /
• v.21 no.10
• /
• pp.977-981
• /
• 2015

We propose a method for the implementation of an EtherCAT communication bus in a Linux-based open source Computerized Numerical Control (CNC) system. Recently, increasingly more CNC systems support real-time Ethernet protocols such as EtherCAT, which is a high-performance industrial communication protocol. For real-time CNC control over an Ethernet-based protocol, an additional layer driver needs to be implemented between the CNC system and the master of industrial communication protocol. Among the various solutions for the connection layer driver, we employ a Hardware Abstraction Layer (HAL) driver based on Linux. The operation of the implemented CNC system is demonstrated and confirmed by Hal Meter, which is used to observe the pins, signals, or parameters of HAL.

• Korean Journal of Materials Research
• /
• v.14 no.6
• /
• pp.413-419
• /
• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• Journal of Korean Society of Water and Wastewater
• /
• v.17 no.4
• /
• pp.519-527
• /
• 2003

Cake layer in crossflow microfiltration(CFMF) can be reduced by coagulation, enhancing membrane flux. This is because enlarging particle size by coagulation increases shear-induced diffusivity and the back-transport of rejected particles. However it is known that the enlarged particles are disaggregated by the shear force of the pump while passing through it. This study is to look at the disaggregation in relation with cake layer reducation. Kaolin and polysulfon hollow fiber microfilter are used for experiment. The reduction of cake resistance by coagulation is observed in a range of 17% to 53% at the various coagulation conditions. The particle size analysis results of the experiments show that aggregated particles in feed are completely disaggregated by pump but re-aggregation of particles occurs in membrane. This suggestes that the re-aggregation of particles is critical to cake reduction and flux enhancement, since the aggregated particles are completely broken. The mechanisms for re-aggregation in membrane are the same with those for coagulation in feed tank. Charge neutralization is better for CCFMF than sweep flocculation although it has two drawbacks in operation.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2016.11a
• /
• pp.97-97
• /
• 2016

Development of advanced Li-ion battery cells with high durability is critical for safe operation, especially in applications to electric vehicles and portable electronic devices. Understanding fundamental mechanism on the formation of a solid-electrolyte interphase (SEI) layer, which plays a substantial role in the electrochemical stability of the Li-ion battery, in a cathode was rarely reported unlike in an anode. Using first-principles density functional theory (DFT) calculations and ab-initio molecular dynamic (AIMD) simulations we demonstrate atomic-level process on the generation of the SEI layer at the interface of a carbonate-based electrolyte and a spinel $LiMn_2O_4$ cathode. To accomplish the object we calculate the energy band alignment between the work function of the cathode and frontier orbitals of the electrolyte. We figure out that a proton abstraction from the carbonate-based electrolyte is a critical step for the initiation of an SEI layer formation. Our results can provide a design concept for stable Li-ion batteries by optimizing electrolytes to form proper SEI layers.

• Journal of the Microelectronics and Packaging Society
• /
• v.8 no.3
• /
• pp.31-36
• /
• 2001

Dielectric material which is suitably designed for the application of the high-temperature electrostatic chucks(HTESCS) has been developed. Electrical resistivities and dielectric constants of the dielectric layer satisfy the demands for the proper operation of HTESC, and coefficient of thermal expansion(CTE) of the dielectric material matches well that of the bottom insulator so that it secures stable structure. In order to minimize particle contaminations, borosilicate glass(BSG) is selected as a bonding layer between dielectric layer and bottom insulator, and silver is used as a electrode. BSG is solidly bonded between upper dielectric and bottom insulator, and no diffusions or reactions are observed among silver electrode, dielectric, and glass layers. The chucking characteristics of the fabricated HTESC are found to be superior to those of the commercialized one.

• Journal of the Korean Ceramic Society
• /
• v.54 no.6
• /
• pp.492-498
• /
• 2017

A thermal barrier coating (TBC) with self-healing property for cracks was proposed to improve reliability during gas turbine operation, including structural design. Effect of healing agent on crack propagation behavior in TBCs with and without buffer layer was investigated through furnace cyclic test (FCT). Molybdenum disilicide ($MoSi_2$) was used as the healing agent; it was encapsulated using a mixture of tetraethyl orthosilicate and sodium methoxide. Buffer layers with composition ratios of 90 : 10 and 80 : 20 wt%, using yttria stabilized zirconia and $MoSi_2$, respectively, were prepared by air plasma spray process. After generating artificial cracks in TBC samples by using Vickers indentation, FCTs were conducted at $1100^{\circ}C$ for a dwell time of 40 min., followed by natural air cooling for 20 min. at room temperature. The cracks were healed in the buffer layer with the healing agent of $MoSi_2$, and it was found that the thermal reliability of TBC can be enhanced by introducing the buffer layer with healing agent in the top coat.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.12
• /
• pp.1056-1061
• /
• 2007

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. The surface morphology was dramatically changed with varying the SiC/Al ratio. When the SiC/Al ratio of 90/1 was used, the step bunching was not observed in this magnification and the ratio of SiC/Al is an optimized range to grow of p-type SiC epitaxial layer. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. 4H-SiC MESFETs haying a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized. It was confirmed that the increase of the negative voltage applied on the gate reduced the drain current, showing normal operation of FET device.

• Proceedings of the IEEK Conference
• /
• 2002.06a
• /
• pp.367-370
• /
• 2002

In this paper, we propose a new node architecture LonWorh control Network for home network system environmint using power line communications. Using conventional Lon Work technology is a many disputable points for home network. LonWork network system needs high-cost development equipment. Moreover, conventional Lon Work system can not implement high-grade algorithms and variety application operation. because of the limitation of processing ability in Neuron chip. For that reason, the proposed structure is applicable to low-cost and more complex applications which are impossible in home network using conventional Lonworks structure. The proposed structure is implemented with some hardware and かone software for power line home network. The physical layer and the MAC layer of the LonTalk protocol within ton Work are implemented in hardware, which decreases the development costs communication processor. The upper of link layer of the LonTalk protocol is implemented with software, which decreases the development costs of software and increases the flexibility of tile system and increases the extension of the system. We verified the commercial feasibility of the proposed system through the power line tests with the existing LonWorks network in home network. As a result, it is concluded that the proposed architecture provides increasing flexibility and decreasing cost of the system.

• Journal of Communications and Networks
• /
• v.6 no.1
• /
• pp.60-67
• /
• 2004

With the fast growth of Internet and a new widespread interest in optical networks, the unparalleled potential of Multi-Protocol Label Switching (MPLS) is leading to further research and development efforts. One of those areas of research is Path Protection Mechanism. It is widely accepted that layer three protection and recovery mechanisms are too slow for today’s reliability requirements. Failure recovery latencies ranging from several seconds to minutes, for layer three routing protocols, have been widely reported. For this reason, a recovery mechanism at the MPLS layer capable of recovering from failed paths in 10’s of milliseconds has been sought. In light of this, several MPLS based protection mechanisms have been proposed, such as end-to-end path protection and local repair mechanism. Those mechanisms are designed for intra-domain recoveries and little or no attention has been given to the case of non-homogenous independent inter-domains. This paper presents a novel solution for the setup and maintenance of independent protection mechanisms within individual domains and merged at the domain boundaries. This innovative solution offers significant advantages including fast recovery across multiple nonhomogeneous domains and high scalability. Detailed setup and operation procedures are described. Finally, simulation results using OPNET are presented showing recovery times of a few milliseconds.