• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.71-77
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• 2015

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.436-442
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• 2016

An electroencephalogram (EEG)-connectome processor to monitor and diagnose mental health is proposed. From 19-channel EEG signals, the proposed processor determines whether the mental state is healthy or unhealthy by extracting significant features from EEG signals and classifying them. Connectome approach is adopted for the best diagnosis accuracy, and synchronization likelihood (SL) is chosen as the connectome feature. Before computing SL, reconstruction optimizer (ReOpt) block compensates some parameters, resulting in improved accuracy. During SL calculation, a sparse matrix inscription (SMI) scheme is proposed to reduce the memory size to 1/24. From the calculated SL information, a small world feature extractor (SWFE) reduces the memory size to 1/29. Finally, using SLs or small word features, radial basis function (RBF) kernel-based support vector machine (SVM) diagnoses user's mental health condition. For RBF kernels, look-up-tables (LUTs) are used to replace the floating-point operations, decreasing the required operation by 54%. Consequently, The EEG-connectome processor improves the diagnosis accuracy from 89% to 95% in Alzheimer's disease case. The proposed processor occupies $3.8mm^2$ and consumes 1.71 mW with $0.18{\mu}m$ CMOS technology.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.6
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• pp.797-803
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• 2012

In this paper, for minimizing the real-time operating load losses of the power transformer, a SCADA optimum operating system was developed, and the economic analyses on the test operation were performed. Transformer loss DB which reflects the economic integration operation criteria was constructed by referring the transformer manufacturer's loss data(iron loss, copper loss). Based on the loss DB, each substation transformer real-time loss was calculated according to the size of the transformer loads, and if integration or separation transformer operating conditions minimizing the loss are met, then a window pops-up and the dispatcher performs the substation equipments operation according to the procedure provided by this system. With the existing SCADA main program, the relation database of the substation facilities and integration/separation operation algorithm were developed and applied to Auto MTR Processor and pconn Processor Task module. Seven stations test data for seven months were analyzed for the economic analyses, and the results showed that Cost-Benefit ratio was 2.64, and IRR(Internal Rate of Return), 36%, which asserted the economic justification of the proposed system.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.1
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• pp.63-73
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• 2001

This paper presents a process and operation planning system with an NC code post-processor for effective machining of press dies for production of cars. Based on the machining features, major parts of press dies are categorized into 15 groups and a standard process plan is defined for each group. The standard process plan consists of a series of processes where a process is defined as a group of operations that can be done with one setup. Details such as cutting tools, cutting conditions, and tool paths are decided at the operation planning stage. At the final stage of process and operation planning, the NC code post-processor we developed adjusts feedrates along the tool path to reduce machining time. The adjustment rule is selected based on the metal removal rate estimated by virtually machining with virtual cutting tool.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1449-1453
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• 1987

A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.788-792
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• 1993

The objective of this study is to develope a satellite dynamic simulator, which can test and analyze the performance of spacecraft attitude control, antenna pointing instruments, communication equipments and spacecraft components under the space environment. The satellite simulator can be used to predict the events such as malfunction and failure of satellites in space during operation and can be used to protect against emergencies. At first, the performance test system of attitude control is investigated which can simulate motion and verify stability of spacecraft. Our system consists of an attitude control main processor and a sub-processor including some real hardwares such as attitude sensors and actuators. In this paper, we describe the procedure of designing and manufacturing the dynamic simulator hardware, which consists of the central processor board, the sub-processor board and the sun sensor, and also communication between the components.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.433-434
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• 2008

In this paper, we present an improved design of the conventional ARM7 processor. It is based on the flip-flop to improve the pipeline performance of the processor. Also for improving the performance, the optimization of functional blocks and a multiplier is carried out. According to the experimental results, the maximum delay-time of functional blocks and the execution cycle of a multiplier is reduced by 33% and 2 cycles compared with a conventional design, respectively. Therefore, it leads to improve an operation speed about 30%.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1213-1216
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• 2003

This paper proposes an 3D graphics rendering processor for portable device. One the most important factor is chip size for portable device, but the conventional 3D graphics rendering processor is not a suitable because the processor needs a lot of multiplication and division units. So the proposed architecture substitutes single precision floating point by 32 bit fixed point, and uses recursive units for the same operation such as color values(z, r, g, b, a) and texture values (s, t, u, v). In this approach, we reduce numbers of multiplications and divisions by 66.1% and 75% respectively at the sacrifice of performance degradation by 2.12%.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.127-135
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• 1994

In this paper we propose an EWLD(Enhanced Weighted Levenshtein Distance) algorithm to organize code-string pattern matching linear array processor based on the mappting to an one-dimensional array from a two-dimensional matching matrix, and design a processing element(PE) of the processor, N PEs are required instead of NS02T in the processor because of the mapping. Data input and output between PEs and all internal operations of each PE are performed in bit-serial fashion. The bit-serial operation consists of the computing of word distance (WD) by comparison and the selection of optimal code transformation path, and takes 22 clocks as a cycle. The layout of a PE is designed based on the double metal $1.5\mu$m CMOS rule. About 1,800 transistors consistute a processing element and 2 PEs are integrated on a 3mm$\times$3mm sized chip.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.913-914
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• 2006

This paper proposes a flexible IED platform which is implemented with a network processor and a DSP. DSP algorithms are downloaded through the embedded Linux based network processor remotely from ethernet. This architecture gives the best flexibility to adaptively accommodate the various algorithms needed in the IED environment. The developed IED platform can simultaneously measure data of the maximum of forty channels. The developed IED platform shows the successful operation, which measures and transfers the 8 channels data of 16bit samples sampled at 3.84kHz per each channel. The detailed performance analysis of the developed IED platform shows the about 10% processing load of CPU running at 533MHz.