• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.10-19
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• 1986

This is the last part of the four-part describing the development of a packet-switched computer communication network named the KORNET. In this paper we describe the design and implementation of the packet assembler/dissassembler (PAD) protocol for the asynchronous channel service, and of the network management softwares. The line processing module-B(LPMB) system supporting the asynchronous line includes a PAD protocol, a packet mode DTE/DCE protocol converting to the X.25 protocol, and the asynchronous receiver/transmitter(ART) software. The network management software is operated in master central processing module(MCPM) which includes virtual circuit management (VCM) managing the user channel, the routing management and the high level protocol for communication between the network management center (NMC) and the network node processor(NNP). In this paper, the design, implementation and operation of the softwares for the above service functions will be described in detail.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.6
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• pp.1081-1086
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• 2023

The rapid growth and increasing complexity of modern networks have highlighted the limitations of traditional network architectures. The emergence of SDN (Software-Defined Network) in response to these challenges has changed the existing network environment. The SDN separates the control unit and the data unit, and adjusts the network operation using a centralized controller. However, this structure has also recently caused a huge amount of traffic due to the rapid spread of numerous Internet of Things (IoT) devices, which has not only slowed the transmission speed of the network but also made it difficult to ensure quality of service (QoS). Therefore, this paper proposes a method of load distribution by switching the IP and any server (processor) from the existing data processing scheduling technique, RR (Round-Robin), to mapping when a large amount of data flows in from a specific IP, that is, server overload and data loss.

• Korean Journal of Remote Sensing
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• v.34 no.6_3
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• pp.1457-1468
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• 2018

The sigma naught (${\sigma}^0$) equation is essential to calculate geo-physical properties from Synthetic Aperture Radar (SAR) images for the applications such as ground target identification,surface classification, sea wind speed calculation, and soil moisture estimation. In this paper, we are suggesting new Kompsat-5 (K5) Radar Cross Section (RCS) and ${\sigma}^0$ equations reflecting the final SAR processor update and absolute radiometric calibration in order to increase the application of K5 SAR images. Firstly, we analyzed the accuracy of the K5 RCS equation by using trihedral corner reflectors installed in the Kompsat calibration site in Mongolia. The average difference between the calculated values using RCS equation and the measured values with K5 SAR processor was about $0.2dBm^2$ for Spotlight and Stripmap imaging modes. In addition, the verification of the K5 ${\sigma}^0$ equation was carried out using the TerraSAR-X (TSX) and Sentinel-1A (S-1A) SAR images over Amazon rainforest, where the backscattering characteristics are not significantly affected by the seasonal change. The calculated ${\sigma}^0$ difference between K5 and TSX/S-1A was less than 0.6 dB. Considering the K5 absolute radiometric accuracy requirement, which is 2.0 dB ($1{\sigma}$), the average difference of $0.2dBm^2$ for RCS equation and the maximum difference of 0.6 dB for ${\sigma}^0$ equation show that the accuracies of the suggested equations are relatively high. In the future, the validity of the suggested RCS and ${\sigma}^0$ equations is expected to be verified through the application such as sea wind speed calculation, where quantitative analysis is possible.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.421-429
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• 2000

In present, ATM integrated switching system has been developed to a mixed modules that complexed switching system including maintenance, operation based on B-ISDN/LAN service and plug-in module, , which runs on workstation computer system. Meanwhile, workstation has HMI operation system feature including file system management, time management, graphic processing, TMN agent function. The workstation has communicated with between ATM switching module and clients. This computer system architecture has much burden messages communication among processes or processor. These messages communication consume system resources which are socket, message queue, IO device files, regular files, and so on. Therefore, in this paper we proposed new performance modeling with this system architecture. We will analyze the system bottleneck and improve system performance. In addition, in the future, the system has many additional features should be migrated to workstation system, we need previously to evaluate system bottleneck and redesign it. In performance model, we use queueing network model and the simulation package is used PDQ and C-program.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.485-495
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• 2000

The parallel computer system that uses parallel program on the application such as a large scale business or complex operation is required. One of crucial operation of parallel computer system is synchronization. A representative method of synchronization is barrier synchronization. A barrier forces all process to wait until all the process reach the barrier and then releases all of the processes. There are software schemes, hardware scheme, or combinations of these mechanism to achieve barrier synchronization which tends to use hardware scheme. Besides, barrier synchronization lets parallel computer system fast because it has fewer start-up overhead. In this paper, we propose a new switch module that can implement fast and fault-tolerant barrier synchronization in hardware scheme. A proposed barrier synchronization is operated not in full-switch-driven method but in processor-driven method. An effective barrier synchronization is executed with inexpensive hardware supports. Therefore, a new proposed hardware barrier synchronization is designed that it is operated in arbitrary network topology. In this paper, we only show comparison of barrier synchronization on Multistage Interconnection Network. This research results in 24.6-24.8% reduced average delay. Through this result, we can expect lower average delay in irregular network.

• Journal of Astronomy and Space Sciences
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• v.17 no.1
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• pp.53-66
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• 2000

We developed low light CCD imaging system using thermoelectric cooling method collaboration with a company to design a commercial model. It consists of Kodak KAF-0401E(768$\times$512 pixels) CCD chip, thermoelectric module manufactured by Thermotek. This TEC system can reach an operative temperature of $-25^{\circ}C$. We employed an Uniblitz VS25s shutter and it has capability a minimum exposure time 80ms. The system components are an interface card using a Korea Astronomy Observatory (hereafter KAO) ISA bus controller, image acquisition with AD9816 chip, that is 12bit video processor. The performance test with this imaging system showed good operation within the initial specification of our design. It shows a dark current less than 0.4e-/pixel/sec at a temperature of $-10^{\circ}C$, a linearity 99.9$\pm$0.1%, gain 4.24e-/adu, and system noise is 25.3e-(rms). For low temperature CCD operation, we designed a TEC, which uses a one-stage peltier module and forced air heat exchanger. This TEC imaging system enables accurate photometry($\pm$0.01mag) even though the CCD is not at 'conventional' cryogenic temperatures(140k). The system can be a useful instrument for any other imaging applications. Finally, with this system, we obtained several images of astronomical objects for system performance tests.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.

• Journal of KIISE:Databases
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• v.33 no.6
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• pp.563-577
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• 2006

A stream processor uses resource sharing method for efficient of limited resource in multiple continuous queries. The previous methods process aggregate queries to consist the level structure. So insert operation needs to reconstruct cost of the level structure. Also a search operation needs to search cost of aggregation information in each size of sliding windows. Therefore this paper uses linear structure for optimization of sliding window aggregations. The method comprises of making decision, generation and deletion of panes in sequence. The decision phase determines optimum pane size for holding accurate aggregate information. The generation phase stores aggregate information of data per pane from stream buffer. At the deletion phase, panes are deleted that are no longer used. The proposed method uses resources less than the method where level structures were used as data structures as it uses linear data format. The input cost of aggregate information is saved by calculating only pane size of data though numerous stream data is arrived, and the search cost of aggregate information is also saved by linear searching though those sliding window size is different each other. In experiment, the proposed method has low usage of memory and the speed of query processing is increased.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.160-167
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• 2005

Among finite filed arithmetic operations, division/inverse is known as a basic operation for public-key cryptosystems over $GF(2^{m})$ and it is computed by performing the repetitive $AB^{2}$ multiplication. This paper presents a digit-serial-in-serial-out systolic architecture for performing the $AB^2$ operation in GF$(2^{m})$. To obtain L×L digit-serial-in-serial-out architecture, new $AB^{2}$ algorithm is proposed and partitioning, index transformation and merging the cell of the architecture, which is derived from the algorithm, are proposed. Based on the area-time product, when the digit-size of digit-serial architecture, L, is selected to be less than about m, the proposed digit-serial architecture is efficient than bit-parallel architecture, and L is selected to be less than about $(1/5)log_{2}(m+1)$, the proposed is efficient than bit-serial. In addition, the area-time product complexity of pipelined digit-serial $AB^{2}$ systolic architecture is approximately $10.9\%$ lower than that of nonpipelined one, when it is assumed that m=160 and L=8. Additionally, since the proposed architecture can be utilized for the basic architecture of crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity and pipelinability.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.31-46
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• 2012

The most critical technology to implement ubiquitous health care is Ubiquitous Sensor Network (USN) technology which makes use of various sensor technologies, processor integration technology, and wireless network technology-Radio Frequency Identification (RFID) and Wireless Sensor Network (WSN)-to easily gather and monitor actual physical environment information from a remote site. With the feature, the USN technology can make the information technology of the existing virtual space expanded to actual environments. However, although the RFID and the WSN have technical similarities and mutual effects, they have been recognized to be studied separately, and sufficient studies have not been conducted on the technical integration of the RFID and the WSN. Therefore, EPCglobal which realized the issue proposed the EPC Sensor Network to efficiently integrate and interoperate the RFID and WSN technologies based on the international standard EPCglobal network. The proposed EPC Sensor Network technology uses the Complex Event Processing method in the middleware to integrate data occurring through the RFID and the WSN in a single environment and to interoperate the events based on the EPCglobal network. However, as the EPC Sensor Network technology continuously performs its operation even in the case that the minimum conditions are not to be met to find complex events in the middleware, its operation cost rises. Moreover, since the technology is based on the EPCglobal network, it can neither perform its operation only for the sake of sensor data, nor connect or interoperate with each information system in which the most important information in the ubiquitous computing environment is saved. Therefore, to address the problems of the existing system, we proposed the design and implementation of USN integration management system. For this, we first proposed an integration system that manages RFID and WSN data based on Session Initiation Protocol (SIP). Secondly, we defined the minimum conditions of the complex events to detect unnecessary complex events in the middleware, and proposed an algorithm that can extract complex events only when the minimum conditions are to be met. To evaluate the performance of the proposed methods we implemented SIP-based integration management system.