• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.200-208
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• 2000

Multi-ports register could shared several instructions at the same time in read operation. We address a formal methods for describing timing analysis and resource restriction in pipeline super scalar process that having multi-Port registers. First, we specify in-order pipeline instructions, and then, extend timing analysis in out-of-order super-scalar. In this case, we find instruction pairs in any cycle which can execute same time, We use ACSR(Algebra of Communicating Shared Resources), a branch of formal methods based on process algebra, for instruction specification and modelling.

• Journal of Advanced Navigation Technology
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• v.5 no.2
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• pp.149-157
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• 2001

A high speed data link capability is one of the critical factors in determining the performance of the spaceborne SAR system with high resolution. It is due to the strict requirement for the real-time data transmission from a series of massive raw image data of spaceborne SAR to the ground station in a limited time of mission. In this paper, based on the data link model characterized by the spaceborne small SAR system, the high rate multi-channel data link module is designed including link storage, link processor, transmitter, and wide-angle antenna. The design results are presented with the performance analysis on the data link budget as well as the multi-mode data rate in association with the SAR imaging mode of operation from high resolution to the wide swath.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1058-1067
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• 2004

Java virtual machine provides code compactness, simple execution engines, and platform-independence which are important features for small devices such as mobile or embedded device, but it has a big problem, such as low throughput due to stack-oriented operation. In this paper hardware lava accelerator targeted for mobile or embedded application is designed to eliminate the slow speed problem of lava virtual machine. The designed lava accelerator can execute 81 instructions of Java virtual machine(JVM)'s opcodes and be used as Java coprocessor of conventional 32-bit RISC processor with efficient coprocessor interface and instruction buffer. It consists of about 14,300 gates and its maximum operating frequency is about 50 Mhz under 0.35um CMOS technology.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.737-742
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• 2009

As increasing emphasis is being placed on user experience design, the RIA technology is widely deployed for user interface and software operation on embedded devices including cell phones and TVs. In particular, RIA-based IPTV enables creation of various interactive contents via sophisticated animation and various input devices. This paper proposes a service framework for emotional contents on broadcast and communication-converged IPTV systems. We design a programming interface extension for IPTV-based flash contents and develop a prototype of flash runtime with the extended programming support. Since the proposed runtime was carefully designed to fully utilize the built-in graphic acceleration hardware in media processor, it supports high resolution graphic animation in resource-constrained IPTV environments.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.3
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• pp.173-183
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• 1998

In this paper, an auto-tuning method for fuzzy controller's membership functions based on the neural network is presented. The neural network emulator offers the path which reforms the fuzzy controller's membership functions and fuzzy rule, and the reformed fuzzy controller uses for speed control of induction motor. Thus, in the case of motor parameter variation, the proposed method is superior to a conventional method in the respect of operation time and system performance. 32bit micro-processor DSP(TMS320C31) is used to achieve the high speed calculation of the space voltage vector PWM and to build the self-learning fuzzy control algorithm. Through computer simulation and experimental results, it is confirmed that the proposed method can provide more improved control performance than that PI controller and conventional fuzzy controller.

• Journal of Digital Convergence
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• v.11 no.4
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• pp.215-220
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• 2013

The super computer calls usually as the super computer in case the computing power of the computer is 20 G flops (GFLOPS) or greater. In the past, the computer equipped with the vector processor (the instrument processing the order having the logic operation and maximum value or minimum value besides the common computer instruction) processing the scientific calculation with the super high speed was installed as the super computer. Recently, cyber attack focuses on supercomputer because if it is being infected, then it will affect hundreds of client PC. Therefore, our research paper analyzed super computer security issues and biometric countermeasure to develop the level of security on super computer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.126-133
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• 2006

This paper describes an AMBA-based IP to perform forward and inverse transform and quantization required in the H.264 video compression standard. The transform and quantization circuit was optimized for area and performance. The AHB wrapper was added to the circuit for the AMBA-based operation. The user of the IP can specify how long the bus may be occupied by the IP and also where the video data are stored in the external memory. The function of the proposed IP based on AMBA Specification was verified on the platform board with Xilinx FPGA and ARM9 processor. We fabricated an MPW chip using $0.25{\mu}m$ standard cells and observed its correct operations on silicon.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.39-46
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• 2004

This paper presents the realization schemes for a multipurpose coherent mono-pulse radar Simulator with extendable features. We developed and installed the TSG(Timing Signal Generator) board which can simulate a mechanically rotate signal of antenna, an operation timing signal of pulse radar and target signal, to operate the simulator without real target in the indoor environment. Also, with the insertion of the radar signal processor, it came to be easy to achieve the addition of radar function algorithms, to rebuild or extend the multi-DSP Architecture into the simulator. Throughout the simulation results, we verified that the designed coherent mono-pulse radar simulator can exactly display a moving target on the realistic monitor(RD 9800).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.105-113
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• 2004

This paper proposes 3D graphics accelerator, especially rendering unit, for portable devices. The existing 3D architecture is not suitable for portable devices because of its huge size. To reduce the size, we use iterative architecture and fixed-point calculation. In this paper, we suggest the format of fixed-point comparing with the result images, and some special technique to control. Finally, it is implemented with FPGA and 0.25um ASIC technology respectively. The ASIC chip can execute 47.88M pixels per second. The size of ASIC chip is 4.9287mm*4.9847mm and the power consumption is 263.7mW with 50MHz operation frequency.

• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.9-12
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• 2005

We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.