• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.2
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• pp.190-199
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• 2014

In the last years, fault problem in power electronics has been more and more investigated both from theoretical and practical point of view. The fault problem can cause equipment failure, data and economical losses. And the analyze system require to ensure fault problem and also rectify failures. The current errors on these faults are applied for identified type of faults. This paper presents technique to detection and identification faults in three-phase voltage source inverter (VSI) by using time-frequency distribution (TFD). TFD capable represent time frequency representation (TFR) in temporal and spectral information. Based on TFR, signal parameters are calculated such as instantaneous average current, instantaneous root mean square current, instantaneous fundamental root mean square current and, instantaneous total current waveform distortion. From on results, the detection of VSI faults could be determined based on characteristic of parameter estimation. And also concluded that the fault detection is capable of identifying the type of inverter fault and can reduce cost maintenance.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.874-875
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• 2007

This paper introduces major potential faults of IPMSM and their simulation realization methods. The faults of IPMSM, generally, contain single-phase open circuit, single-phase or 3-phase short circuit, and uncontrolled generation. When different fault occurs, the circuit of total system including motor and inverter also will be changed. Therefore, it is necessary to analyze and establish independent model for each kind of fault. In this paper, first, the drive circuit is analyzed as different fault type. Then, the corresponding simulation results solved in Simulink@MATLAB are given. The absence of experiment results leads that the veracity of simulation results can not be verified, but the tendency will be explained by theory analysis.

• Journal of Power Electronics
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• v.9 no.6
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• pp.949-959
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• 2009

This paper presents a systematic investigation of the fault-mode behaviors of matrix converter systems. Knowledge about converter behaviors after fault occurrence is important from the standpoint of reliable system design, protection and fault-tolerant control. Converter behaviors have been, in detail, examined with both qualitative and quantitative approaches for key fault types, such as switch open-circuited faults and switch short-circuited faults. Investigating the fault-mode behaviors of matrix converters reveals that converter operation with switch short-circuited faults leads to overvoltage stresses as well as overcurrent stresses on other healthy switching components. On the other hand, switch open-circuited faults only result in overvoltage to other switching components. This study can be used to predict fault-mode converter behaviors and determine additional stresses on remaining power circuit components under fault-mode operations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.100-105
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• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.182-187
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• 2015

In the three-phase power system, when any one-phase or two-phases is open-phase, the unbalanced current flows and the single-phase power supplies to three-phase loads. Specially, motor coil and transformer coil receive over-current. As a result, great damage as well as electrical fire can occur to the power system. In order to improve these problems, this paper proposes that an open-phase detection device is designed by a new algorithm using electric potential difference between the resultant voltage of neutral point and ground, and a control circuit topology of open-phase protector is composed of highly efficient semiconductor devices. It improves response speed and reliability. The control algorithm circuit also operates the cut-off of a conventional residual current protective device (RCD) which flows an enforced leakage current to ground wire at open-phase accident. Furthermore, time delay circuit is added to prevent the incapable operation of open-phase protector about instantaneous open-phase not open-phase fault. The time delay circuit improves more reliability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.4
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• pp.313-319
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• 2019

Induction motors connected with a three-phase AC system may malfunction due to reverse phase or open phase faults. Conventional overcurrent relays and overheating relays are used to prevent such accidents; however, their drawbacks include a low response speed and false operation. Therefore, in this study, a digital relay for the reverse-open phase was designed and fabricated. This relay can detect the reverse phase and open phase faults and send a trigger signal to the control circuit. The proposed relay was developed based on a microcontroller. The detection times of the reverse phase and open phase were verified as 320ms and 80ms, respectively. Compared with conventional relays that only protect the motor from one type of fault, the proposed relay can detect both, reverse phase and open phase faults. In addition, the fault detection, identification criterion, and trigger signal patterns can be modified by programming according to the requirements of users.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2000-2003
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• 2002

In this paper, an IC chip of a cell- network type circuit constructed with 1-dimensional chaos circuits is reported. The circuit, is designed by sing switched-current (Sl) techniques. In the proposed circuit, by controlling connections of cells, an S- dimensional circuit (S ＝ 1, 2, 3,…) and a synchronization system can be constructed easily. Furthermore, in spite of faults of a few cells, the circuit can reconstruct above-mentioned systems only to change connections of cells. This feature will open up new vista for engineering applications which are used in a distance place such as space, deep sea, etc. since it is difficult to repair faults of these application systems. To investigate the characteristics of the circuit, SPICE simulations are performed. The VLSI chip is fabricated from the layout design using a CAD tool, MAGIC. The proposed circuit is integrable by a standard 1.2 $\mu\textrm{m}$ CMOS technology.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.3
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• pp.217-224
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• 2013

This paper presents a diagnostic method for a sparse matrix converter that detects faults in any single switch or a pair of switches. The sparse matrix converter is functionally equivalent to the standard matrix converter but has a reduced number of switches. The proposed diagnostic method is based in the measurement of input and output currents. The currents have respective characteristic according to the location of faulty switches. This method not only detects the switches of open-circuit fault but identifies the location of the faulty switching devices without complicated calculations. The simulation and experimental results verify that, based on the proposed method, the fault of sparse matrix converter can be easily and fast detected.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.