• 전기학회논문지
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• 제64권1호
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• pp.182-187
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• 2015

In the three-phase power system, when any one-phase or two-phases is open-phase, the unbalanced current flows and the single-phase power supplies to three-phase loads. Specially, motor coil and transformer coil receive over-current. As a result, great damage as well as electrical fire can occur to the power system. In order to improve these problems, this paper proposes that an open-phase detection device is designed by a new algorithm using electric potential difference between the resultant voltage of neutral point and ground, and a control circuit topology of open-phase protector is composed of highly efficient semiconductor devices. It improves response speed and reliability. The control algorithm circuit also operates the cut-off of a conventional residual current protective device (RCD) which flows an enforced leakage current to ground wire at open-phase accident. Furthermore, time delay circuit is added to prevent the incapable operation of open-phase protector about instantaneous open-phase not open-phase fault. The time delay circuit improves more reliability.

• 지질공학
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• 제15권3호
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• pp.349-363
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• 2005

울산단층 동부지역에는 제4기로 추정되는 미고결 퇴적층을 절단하며 파쇄대 와 단층비지를 수반하는 제4기 단층이 여러 곳에서 발견되고 있다. 본 연구에서는 제4기 단층비지대의 성분변화, 체적변화, 실리카의 손실 그리고 유체-암석비를 XRF, XRD, EPMA를 이용하여 계산하였다. 단층비지의 성분변화는 모암에 비해 단층비지대에서 $SiO_2,\;K_2O,\;Na_2O$는 감소하고, $Al_2O_3,\;MgO,\;P_2O_5,\;Fe_2O_3,\;MnO,\;CaO,\;LOI$는 증가한다. 단층별 체적감소는 개곡 제1단층 $56\%$, 개곡 제2단층 $22\%$, 신계단층 $34\%$, 마동단층 $8\%$, 원원사단층 $2\%$, 진현단층 $53\%$이다. 체적감소, 실리카 손실, 유체-암석비가 낮게 나타난 마동단층과 원원사단층 비지대는 유체활동에 대하여 닫힌계 이 고, 체적감소, 실리카 손실, 유체-암석비가 높은 개곡 제1단층과 진현단층의 비지대는 유체 활동의 통로로 작용한 열린계였을 것으로 볼 수 있다. 단층의 유체-암석 체적비는 모든 단층에서 $10^2\sim10^4$로 나타나지만 기질의 함량이 각각 $88\%$와 $77\%$로 높고 체적감소가 큰 개곡 제1단층과 진현단층에서 가장 높게 나타난다. 따라서 이들 단층에서 유체의 활동이 가장 활발하였다.

• ETRI Journal
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• 제39권4호
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• pp.605-613
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• 2017

Simulated fault injection (SFI) is widely used to assess the effectiveness of fault tolerance mechanisms in safety-critical embedded systems (SCESs) because of its advantages such as controllability and observability. However, the long test time of SFI due to the large number of test cases and the complex simulation models of modern SCESs has been identified as a limiting factor. We present a method that can accelerate an SFI tool using a checkpoint forwarding (CF) technique. To evaluate the performance of CF-based SFI (CF-SFI), we have developed a CF mechanism using Verilog fault-injection tools and two systems under test (SUT): a single-core-based co-simulation model and a triple modular redundant co-simulation model. Both systems use the Verilog simulation model of the OpenRISC 1200 processor and can execute the embedded benchmarks from MiBench. We investigate the effectiveness of the CF mechanism and evaluate the two SUTs by measuring the test time as well as the failure rates. Compared to the SFI with no CF mechanism, the proposed CF-SFI approach reduces the test time of the two SUTs by 29%-45%.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 1988년도 학술세미나 강연집
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• pp.3-67
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• 1988

Model studies on the response of homgeneous earth embankment dams subjected to strike-slip fault movement have been penomed via centrifuge and finite element analysis. The centrifuge model tests have shown that crack development in earth embankment experiences two major patters: shear failure deep inside the embankment and tension failure near the surface. The shear rupture zone develops from the base level and propagates upward continuously in the transverse direction but allows no open leakage chnnel. The open tensile cracks develop near the surface of the embankment, but they disappear deep in the embankment. The functional relationship has been developed based on the results of the centrifuge model tests incorporating tile variables of amount of fault movement, embankment geometry, and crack propagation extent in earth des. This set of information can be used as a guide line to evaluate a "transient" safety of the duaged embankment subjected to strike-slip fault movement. The finite element analysis has supplemented the additional expluations on crack development behavior identified from the results of the centrifuge model tests. The bounding surface time-independent plasticity soil model was employed in the numerical analysis. Due to the assumption of continuum in the current version of the 3-D FEM code, the prediction of the soil structure response beyond the failure condition was not quantitatively accurate. However, the fundamental mechanism of crack development was qualitatively evaluated based on the stress analysis for the deformed soil elements of the damaged earth embankment. The tensile failure zone is identified when the minor principal stress of the deformed soil elements less than zero. The shear failure zone is identified when the stress state of the deformed soil elements is at the point where the critical state line intersects the bounding surface.g surface.

• 전자공학회논문지B
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• 제29B권9호
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• pp.1-7
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• 1992

This paper proposes a built-in self-test tchnique for CMOS circuits. To detect a stuck-open fault in CMOS circuits, two consequent test patterns is required. The ordered pairs of test patterns for stuck-open faults are generated by feedback shift registers of extended length. A nonlinear feedback shift register is designed by the merging method and reordering algorithms of test patterns proposed in this paper. And a new multifunctional BILBO (Built-In Logic Block Observer) is designed to perform both test pattern generation and signature analysis efficiently.

• 전력전자학회논문지
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• 제16권5호
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• pp.457-465
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• 2011

본 논문에서는 3상 다이오드 정류기의 고장에 따른 해석 및 고장 판별 기법을 제안한다. 입력전원이나 다이오드소자에 고장이 발생하게 되면 출력 직류단 전압에 큰 맥동을 유발하며 이는 인버터 시스템의 제어 성능을 저하시킬 뿐만 아니라 커패시터의 수명 단축을 야기한다. 본 논문에서는 입력측의 지락 사고 및 다이오드 개방 사고 시의 직류단 전압 특성을 분석하고, 계통주파수의 6배에 주파수마다 측정된 직류단의 순시전압을 직류단 평균 전압과 비교함으로서 고장의 유무 및 종류를 판별하는 알고리즘을 제안하였다. 제안한 알고리즘은 직류단 전압 센서만을 이용하므로 구현이 간단하고 고장 진단을 위한 추가적인 하드웨어가 요구되지 않는다. 실험과 시뮬레이션을 통해 제안한 고장 진단 알고리즘의 타당성을 검증하였다.

• 전자공학회논문지A
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• 제31A권10호
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2009년도 정보 및 제어 심포지움 논문집
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• pp.19-21
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• 2009

The reflectometry for locating the fault at a cable is the same as a problem estimating the time delay between the incident and the reflected signals. In this paper, we propose a method for estimating the time delay between the two signals. The proposed method is based on the modeling of the Gaussian enveloped linear chirp signal in the Gaussian noise environment. The phase and the instantaneous frequency of the received signal are estimated by linear Kalman filtering. From the estimated instantaneous frequency, we can measure the time interval between the center frequencies of the incident and the reflected signals. The time interval is the same as the time delay between the incident and the reflected signals. In a simulation assuming that the cable has open fault at the end of the cable, the proposed method showed a good result in estimating the time delay.

• 전기학회논문지
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• 제63권12호
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• pp.1710-1715
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• 2014

In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2015년도 제46회 하계학술대회
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• pp.1066-1067
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• 2015

This paper presents a diagnosis method for the detection and location of open-short switch faults in the three-phase power conditioning system. A method for switch fault diagnosis on the power conditioning system is proposed, based on the concordia transform. The switch fault types and locations on power conditioning system are diagnosed by a method in which analyze the d-q current vector locus and current pattern. The Simulation results confirm the proposed diagnostic method.