• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3178-3180
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• 2000

In this thesis, a controller which is appropriate for uses of scanner with small error and high speed response is proposed. Recently the application field of scanner is on increase. In case of applying to laser marking, the error of scanner has bad effect to quality. Also it can make difficulties in applying laser show that makes images, unless the high speed response is not realized. For these reasons, a controller that can adjust error and response is need. Because scanner must respond to step input that is put between a few millisecond and hundreds of microsecond with small revolution angle ranges, it is advantageous to have small inertia and large torque. First, the property of scanner is treated, and then using Op-amp and passive components and applying feedback compensation PID controller to design, the effects by controller coefficients are introduced.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.2
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• pp.47-54
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• 1982

In this paper, a improved per-channel PCM Coder with 1-bit interpolation is proposed. The coder converts a telephone signal to 15-segments u-law PCM signal of a large dynamic range. The A/D conversion technique of the proposed converter requires a feedback loop around a quantizer operates at high speed, and a accumulater for accumulating the quantized values to provide PCM outputs. To obtain both linear and compressed PCM signals a improved table look-up method is presented. The operations of the proposed converter are certified through the experiments to be good. The experimental circuit comprises TTL logic gates, a resistive D/Z converter and a simple differential amplifier. From the results of the experiments, it is known that the proposed converter has many advantage to be adopted economically for per-channel onverter used in rural area service.

• Journal of the Korean Solar Energy Society
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• v.33 no.6
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• pp.92-97
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• 2013

This paper proposes DC offset current compensation method of transformerless fuel cell/PV PCS. DC offset current is generated by the unbalanced internal resistance of the switching devices in full bridge topology. The other cause is the sensitivity of the current sensor, which is lower than DSP in resolution. If power converter system has these causes, the AC output current in the inverter will generate the DC offset. In case of transformerless grid-connected inverter system, DC offset current is fatal to grid-side, which results in saturating grid side transformer. Several simulation results show the difficulties of detecting DC offset current. Detecting DC offset current method consists of the differential amplifiers and PWM is compensated by the output of the Op amp circuit with integrator controller. PSIM simulation verifies that the proposed method is simpler and more effective than using low resolution current sensor alone.

• Journal of the Korean Institute of Intelligent Systems
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• v.17 no.4
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• pp.569-574
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• 2007

최근 많은 광대역 유무선 통신 응용분야에서 OFDM(Orthogonal Frequency Division Multiplexing) 방식을 표준기술로 채택하고 있다. OFDM 방식의 고속 무선 데이터 통신을 위한 FFT 프로세서는 일반적으로 DSP(Digital Signal Processing)로 구현되었으나, 큰 전력 소비를 필요로 한다. 따라서, OFDM 통신방식의 단점인 전력문제를 보완하기 위해서 전류모드 FFT LSI가 제안되었고, 저소비전력 전류모드 FFT LSI를 동작시키기 위해서는 전류모드를 전압모드로 바꾸는 VIC(Voltage to Current Converter) 그리고 다시 전류모드를 전압모드로 바꾸어 주는 IVC(Current to Voltage Converter)가 필요하다. 그러나, OP-AMP로 구현되는 종래의 IVC는 회로규모가 크고, 전력소비가 크며, LSI 내에 크고 정확한 높은 저항을 필요로 한다. 또한 전류모드신호처리에서 많이 이용되는 Current Mirror 회로 등의 출력단자로부터 전류신호를 입력받은 경우, 입력단자간의 전위차가 발생하며, DC offset 전류가 발생하는 등의 문제점을 갖는다. 따라서 본 연구에서는 저전력 동작이 가능하고, 향후, single chip 응용이 가능한 IVC를 $0.35{\mu}m$ 공정에서 설계함으로서, $0.35{\mu}m$ 공정에서의 전류모드 FFT LSI의 전압모드 출력이 가능해졌다 설계된 IVC는 FFT LSI의 출력이 디지털신호로 환산한 ${\pm}1$인 점을 감안하여, 전류모드 FFT LSI의 출력이 $13.65{\mu}A$ 이상일 때에 3.0V의 전압을 출력하고, FFT LSI의 출력이 $0.15{\mu}A$ 이하일 때에 0.5V 이하의 전압을 출력하도록 하였으며, IVC의 총 소비전력은 약 1.65mV이하로 평가되었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.11
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• pp.872-879
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• 2017

This work presents a cable fault monitoring system based on the differential frequency domain reflectometry using a compact impedance analyser which is composed of a direct digital synthesizer, an op amp and a gain/phase detector with a micro controller. The proposed system can replace expensive vector network analysers for frequency domain reflectometry and therefore be deployed in sensor networks for long term multi-point cable monitoring. Effectiveness of the system is experimentally confirmed by diagnosing the status of the power cable.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.446-450
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• 2011

Tunable SC(Switched Capacitor) bandpass ${\Sigma}-{\Delta}$(Sigma-Delta) modulator used in wireless system receiver occurs a signal attenuation according to tuning of center frequency in signal bandwidth. In this paper, tunable bandpass 4th order SC bandpass ${\Sigma}-{\Delta}$ modulator with novel structure is proposed for rejection of signal attenuation in signal bandwidth. The existing structure uses a ten variable coefficient values for rejection of signal reduction in the modulator. But the proposed structure only use a two variable coefficient values for rejection of signal attenuation in the modulator. Also, an adder and comparator is replaced with a comparator having 4 inputs in the modulator. Therefore, the existing structure has one more OP-AMP. The purposed modulator was designed in $0.18\;{\mu}m$ CMOS technology. The resolution of the modulator within 310 kHz bandwidth and 40 MHz sampling frequency under 6.67 MHz, 10 MHz and 13.33 MHz intermediate frequency are over 10 bit.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.2120-2132
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• 1997

A layout automation system for analog integrated circuits is proposed. The implemented system performs full-custom analog layout under the analog layout constraints. In order to overcome the demerits of conventional analog layout systems, parameterized module library is proposed. The system can support complex analog layout modules, resulting in a maximum expandability of the system. Moreover, modified dynamic multi-path algorithm is developed by enhancing the conventional Dijkstra algorithm. Several benchmark circuits such as comparator, op amp, and filter was tested by the system. Layout results compared to OPASYN show well-merging layout and interdigitized layout module.

• Journal of the Korea Institute of Military Science and Technology
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• v.19 no.3
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• pp.379-386
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• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.347-348
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• 2007

On-chip micro humidity sensor, using $CN_x$ films for the sensing material, was designed, simulated, and fabricated with Op amp based readout circuit and diode temperature sensors. To compensate the temperature and other gases, two methods were applied. One is wheatstone-bridge with reference FET that eliminates other undesirable chemical species, and the other is a diode temperature sensor to compensate the temperature effect. $CN_x$ film can be a new humidity sensing material, and has a strong potential to adapt to smart sensors or multi-sensors using MEMS or nano-technology. A particular design technology for integration of sensors and systems together was proposed that whole fabrication process could be achieved by a standard CMOS process.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.917-918
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• 2007

The former earth leakage breaker is operating by total leakage current which is the vector-sum of resistive leakage current and capacitive leakage current. However, the electric disaster like the electric shock and fire is caused mainly by resistive leakage current. Therefore, the earth leakage breaker is ideal when it is operating by resistive leakage current. In this paper, the theory for finding the component of resistive leakage current from total leakage current is suggested and it is embodied to actual circuit. The resistive leakage current can be found by integrating the total leakage current during half cycle of line voltage. Thus, we can simply find resistive leakage current by using OP-AMP integrators, and we can confirm that the resistive leakage current is computed exactly from total leakage current obtained by resistive leakage current and capacitive leakage current. The results that the earth leakage breaker is operating within regular interrupt time are verified when the former earth leakage breaker's controller circuit is replaced by the proposed controller circuit.