• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1475-1482
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• 2009

In this paper, a computer simulation is developed for isotachophoretic protein separation in a serpentine micro channel for optimal lab on a chip design using 2D Finite Element Method. This 2D ITP model is composed of 5 components such as hydrochloric acid as Leader, caproic acid as terminator, acetic acid and benzoic acid as two proteins, and histindine as background electrolyte. The computer model is based on mass conservation equation for 5 components, charge conservation equation for electric potential, and electro neutrality condition for pH calculation. For the validation of the 2D spatial ITP model, the results are compared with the Simul5 developed by Bohuslav Gas Group. The simulation results are in a good agreement in a ID planar channel. This proves the precision of our model. The 2Dproteinseparation is conducted in a 2D curved channel for Lab on a chip design and dispersions of proteins are revealed during the electrophoretic process in a curved shape.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.96-99
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• 2002

This paper describes the implementation of a SoC(system on a Chip) for a mult communication terminal in ISDN network and also reviews the developed software struct service procedures which are working on the SoC. And finally this paper descr： of an ISDN terminal equipment using the implemented SoC and terminal software.

• Journal of information and communication convergence engineering
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• v.17 no.4
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• pp.279-284
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• 2019

This paper presents processing-node status-based message scattering and gathering algorithms for multi-processor systems on chip to reduce the communication time between processors. In the message-scattering part of the message-passing interface (MPI) scatter function, data transmissions are ordered according to the proposed linear algorithm, based on the processor status. The MPI hardware unit in the root processing node checks whether each processing node's status is 'free' or 'busy' when an MPI scatter message is received. Then, it first transfers the data to a 'free' processing node, thereby reducing the scattering completion time. In the message-gathering part of the MPI gather function, the data transmissions are ordered according to the proposed linear algorithm, and the gathering is performed. The root node receives data from the processing node that wants to transfer first, and reduces the completion time during the gathering. The experimental results show that the performance of the proposed algorithm increases at a greater rate as the number of processing nodes increases.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.990-994
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• 2003

This paper describes the VoIP(Voice over Internet Protocol) SoC(System on Chip) Design and the test board development for the function verification to support voice communication services using Internet. To implement the simple system of configuration, we designed the VoIP SoC which have ARM922T of 32bit microprocessor, IP network interface, voice signal interface, various user interface function. Also we developed test program and communication protocol to verify the function of this chip. We used several tools of design and simulation, developed and tested a test board with Excalibur which includes ARM922T microprocessor and FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.273-279
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• 2001

This paper describes a design and implementation of ISDN system on a chip which provides ISDN service and used to develop a low-price multimedia communication terminal. This ISDN SOC is an ISDN system control chip which has 32bit RISC processor, and it includes ISDN S interface transceiver, G.711 voice CODEC, PC interface for data communication, ISDN protocol which includes Q.931 call control protocol and internet protocol. It provides good solution to develope ISDN terminal equipment and ISDN terminal adaptor which connected with basic rate interface, because it minimize external peripheral devices.

• Journal of Information Processing Systems
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• v.3 no.1
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• pp.16-20
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• 2007

This paper describes the development of the sensor interface and driver program for a point of care (POC) device. The proposed pac device comprises an ARM9 embedded processor and eight-channel sensor input to measure various bio-signals. It features a user-friendly interface using a full-color TFT-LCD and touch-screen, and a bluetooth wireless communication module. The proposed device is based on the system on a programmable chip (SOPC). We use Altera's Excalibur device, which has an ARM9 and FPGA area on a chip, as a test bed for the development of interface hardware and driver software.

• Journal of information and communication convergence engineering
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• v.19 no.3
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• pp.175-179
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• 2021

Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover, a hardware-based FI can cause permanent damage to the target system, because the actual circuit cannot be restored. Accordingly, we propose a simulation-based FI framework based on the Verilog Procedural Interface for measuring the failure rates of SoCs caused by soft errors. We execute five benchmark programs using an ARM Cortex M0 processor and inject soft errors using the proposed framework. The experiment has a 95% confidence level with a ±2.53% error, and confirms the reliability and feasibility of using proposed framework for fault analysis in SoCs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.215-221
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• 2016

In this thesis we introduce a large quantity of input interface system using a low cost single chip microcontroller which is consists of walking board with 1600 switches, RS485 communication for switch data communication and PC application software for walking pattern analysis. When a pedestrian walks on the walking board, the pattern analysis of foot pressed switches can be utilized on diverse divisions of sports and industry such as walking physical therapy, dancing, a large quantity of sensors interface system, etc.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.96-101
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• 2015

This paper describes a design and implementation of the NFC bridge chip which performs interface between kinds of devices and mobile phones including NFC controller through NFC communication. The NFC bridge chip consists of the digital part and the analog part which are based on NFC Forum standard. Therefore the chip treats RF signals and then transforms the signal to digital data, so it can interface kinds of devices with the digital data. Especially the chip is able to detect RF signals and then wake up the host processor of a device. The wakeup function dramatically decreases the power consumption of the device. The carrier frequency is 13.56MHz, and the data rate is up to 424kbps. The chip has been fabricated with SMIC 180nm mixed-mode technology. Additionally an NFC bridge chip application to the blood glucose measurement system is described for an application example.

• International Journal of Internet, Broadcasting and Communication
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• v.7 no.2
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• pp.161-167
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• 2015

The performance of high power LEDs highly depends on the junction temperature. Operating at high junction temperature causes elevation of the overall thermal resistance which causes degradation of light intensity and lifetime. Thus, appropriate thermal management is critical for LED packaging. The main goal of this research is to improve thermal resistance by optimizing and comparing nano-pore silicon-based thermal substrate to insulated metal substrate and direct bonded copper thermal substrate. The thermal resistance of the packages are evaluated using computation fluid dynamic approach for 1 W single chip LED module.