• Journal of the Korea Convergence Society
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• v.10 no.11
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• pp.95-100
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• 2019

In this paper, autonomous vehicles of service with existing vehicle accident for the prevention of the vehicle communication technology, self-driving techniques, brakes automatic control technology, artificial intelligence technologies such as well and developed the vehicle accident this occur to death or has been techniques, can prepare various safety cases intended to minimize the injury. In this paper, it is a study to secure safety in autonomous vehicles. This is determined according to spatial factors such as chip signals for general low-power short-range wireless communication and micro road AI. On the other hand, in this paper, the safety of boarding is improved by checking the signal from the electronic chip, up to "recognition of the emotion from residence time in the sensing area" to the biological electronic chip. As a result of demonstrating the reliability of the world countries the world, inducing safety autonomous system of all passengers in terms of safety. Unmanned autonomous vehicle riding and commercialization will lead to AI systems and biochips (Verification), linked IoT on the road in the near future, and the safety technology reliability of the world will be highlighted.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.1525-1527
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• 2013

본 논문에서는 저시력자의 개선된 독서 환경을 제공하는 시각보조기기를 위한 실시간 영상처리 SoC(System on Chip) 하드웨어 구조 설계에 대해서 기술한다. 기존의 시각보조기기는 화면 영상이 실제 움직임보다 늦게 출력되는 잔상 현상이 발생하며, 색 변환 기능도 제한적이다. 따라서 본 논문에서 제안하는 실시간 영상처리 SoC 하드웨어 구조는 데이터 연산을 최소화함으로써 잔상 현상이 감소되며, 저시력자를 위한 다양한 색상 모드를 지원한다. 제안하는 영상처리 SoC 하드웨어 구조는 Core-A 모듈, Memory Controller 모듈, AMBA AHB bus 모듈, ISP(Image Signal Processing) 모듈, TFT-LCD Controller 모듈, VGA Controller 모듈, CIS Controller 모듈, UART 모듈, Block Memory 모듈로 구성된다. 시각보조기기를 위한 실시간 영상처리 SoC 하드웨어 구조는 Virtex4 XC4VLX80 FPGA 디바이스를 이용하여 검증하였으며, TSMC 180nm 셀 라이브러리로 합성한 결과 동작주파수는 54MHz, 게이트 수 197k이다.

• ETRI Journal
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• v.38 no.6
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.344-352
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• 2020

Covertness and performance are very important design goals in the underwater communications. To satisfy both of them, we proposed efficient underwater communication model which combined multiband and direct sequence spread spectrum method in order to improve performance and covertness simultaneously. Turbo coding method with 1/3 coding rates is used for channel coding algorithm, and turbo equalization method which iterately exchange probabilistic information between equalizer and decoder is used for receiver side. After optimal threshold value was set in Rake processing, this paper analyzed the performance by varying the number of chips were 8, 16, 32 and the number of bands were from 1 to 4. Through the simulation results, we confirmed that the performance improvement was obtained by increasing the number of bands and chips. 2~3 dB of performance gain was obtained when the number of chips were increased in same number of bands.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.681-684
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• 2008

In this paper, triple band mobile chip antenna for DCS($1.71{\sim}1.88GHz$) / PCS($1.75{\sim}1.87GHz$) / UPCS($1.85{\sim}1.99GHz$) on PCB Layout is fabricated. As designed and fabricated antenna is loaded PCB layout, that plate a both side at two independence patterns(upper & lower) to reduce the size and a capacitor for DCS, PCS, UPCS band is proposed. The antenna has a small size of about $19mm{\times}4mm{\times}1.6mm$, narrow bandwidth which is the defect of chip antenna is improved. Bandwidth of fabricated antenna to VSWR less than 2 is satisfied and all bandwith is acquired 15.1 % at $1.71GHz{\sim}1.99GHz$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2210-2216
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• 2007

In this paper, triple-band plastic chip antennas for mobile terminal are investigated. Plastic chip antenna is composed of Foamex material with circle of PVC(Polyvilyl chloride). For its electric characteristics, the dielectric constant is 1.9, the insulation intensity is 112KV/cm. Plastic chip antennas are don't tend to break easily against to external shock, have more gain and efficiency than ceramic chip antennas. Triple-band plastic chip antennas of four type are implemented and experimented. From the experiments results, the antenna resonate at the triple-band, the gain of the antennas has about above -2dB, the pattern is ommidirectional the same as the conventional antennas. So, the antennas realized with Foamex material will be application for mobile phone antenna operated at the triple band which is cellular band and Korea-PCS band and ISM band or the antenna for other wireless communication system.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1521-1523
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• 2002

본 논문에서는 1.58 ${\times}$ 0.82 ${\times}$ 0.94 $mm^3$크기의 H 형태의 솔레노이드형 RF 칩 인덕터를 코일의 직경과 권선수를 변화시키면서 제작하였고, 그들의 고주파 성능을 비교 분석하였다. 저손실 $Al_2O_3$재료를 코아로 $30{\mu}m{\sim}40{\mu}m$의 여러 직경을 가진 Cu를 코일로 사용하였다. 인덕터의 인덕턴스(L), 품질계수(Q), 저항(R), 임피던스(Z) 그리고 커패시턴스(C) 등의 주파수 특성은 HP4291B로 측정하였다. 실험결과 동일권선수에 대해 코일직경이 자을수록 L, Q, R, 그리고 Z등이 증가하였고, 그 증가폭은 권선수가 클수록 커지는 경향이 있음을 알 수 있었다. 그러나 코일직경이 작을수록 기생 커패시턴스 효과가 빨리 나타나 자기 공진주파수 효과가 감소하는 경향을 보이고 있음을 확인하였다. 코일직경이 $3{\mu}m$이고 권선수가 6인 경우에 대표적인 값들은 다음과 같다. L=31.4nH(at 250MHz), Q=49.6(at 700MHz), R=0.362${\Omega}$(at 1MHz)

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.389-393
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• 2003

This paper presents circuit modeling and characterization of silicon-based on-chip integrated inductors in Giga Hertz range for wireless communication products. We compare several different designs of on-chip inductors for self-resonant frequency and quality factor. The measurement data could be used as a design guide for manufacturing practical spiral inductors for wireless applications. We provide the equivalent inductor circuit parameters from the actual measurement data.