• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.1137-1140
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• 1999

In this thesis, we research about Communication System Construction and Test-Bed Realization Method and Software’s Design with written program into Embedded Micro Controller’s restricted memory region using a DSP Chip to deal with mainly high speed communication. Tools used for modern communication network control use TI or AMD general chip class, but nevertheless responsibility for the point at issue, Analog Device is architecture design model moderated for small communication system. In this thesis, we present extended model, and realize basic case.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.83-93
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• 2014

It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.1
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• pp.64-69
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• 2005

In this paper, we analyzed the nonlinear performance on the DS/CDMA Communication System. At the $BER=10^{-4}$, uniform chip waveforms have similar performance in the linear channel. However, non-uniform chip waveforms have about more 0.5[dB] power gain than the conventional raised-cosine chip waveforms. In the nonlinear HPA, non-uniform chip waveforms have worse BER performance than the uniform chip waveforms because of the high PAPR. In other words, non-uniform chip waveforms show similar performance as uniform chip waveforms if IBO (input back on) of 15[dB] is given.

• Journal of the Korea Society of Computer and Information
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• v.21 no.5
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• pp.65-71
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• 2016

Bluetooth technology(BT) is a standard for short distance wireless communication and widely used to connect and control various electronic and telecommunication devices without wires, where CSR8670 chip is generally adopted. These BT devices are required to comply with BT specification and the equipments for conformance test are also important. However, the existing BT testing methods have inconvenience in that they are mostly time-consuming procedure due to not only repetitive execution for each evaluation element but also error-prone nature of manual experiments. This paper proposes an automated BT communication test method using CSR8670 chip, which solves the problems related to manual testing methods. The proposed method can reduce the development period of BT products and guarantee the quality improvement owing to the exact system error detection capability.

• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.28-36
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• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.56-65
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• 2009

As increasing the number of IPs integrated in a single chip and requiring high communication bandwidth on a chip, the trend of SoC communication architecture is changed from bus- or crossbar-based architecture to packet switched network architecture, NoC. However, highly complex control logics in routers require multiple cycles to switch packet. In this paper, we design low complex router to improve the communication latency. Our NoC design is verified by simulation platform modeled by ESL tool, SoC Designer. We also evaluate our NoC design comparing to the previous NoC architecture based on VC router. Our results show that our NoC architecture has less communication latency, even small throughput degradation (about 1-2%).

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.2
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• pp.97-104
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• 2011

This paper deals with the quick and precise disaster prevention automation system (DPAS) based on information communication technology (IT) that detects fire and disasters in the building automatically and quickly and then activates the facilities to extinguish fire and disasters, monitoring such situation in a real time through wire-wireless communication network. The proposed DPAS is applied a programmable logic controller (PLC) of one-chip type which is smallsize and lightweight and also has highly sensitive-precise reliabilities. The one-chip type PLC analyzes detected signals from sensors in a case of fire and disasters, then activates fire extinguishing facilities for rapid suppression. The detected data is also transferred to a remote situation room through wire-wireless network of RS232c and bluetooth communication. The transferred data sounds an emergency alarm signal, and operates a monitoring program. The proposed DPAS based on IT will minimize the life and wealth loss from rapid measures while prevents fire and disasters.