• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.80-87
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• 2003

On this study, an End-Effector for the 300mm wafer transfer robot System is newly suggested. It is a mechanical type with $180^{\circ}$ rotating ranges and is composed of 3-point arms, two plate springs and single-axis DC motor. It is controlled by microchip for the DC motor control. To design, relationships on the gripping force and the wafer deformation is analyzed by FEM analysis. Criterion on gripping force of a suggested End-Effector is confirmed as $255 ~ 274g_f$ from experimental results. From experimented results on repeatable position accuracy, gripping force and gripping cycle times in a wafer cleaning system, we confirmed that the suggested End-Effector is well satisfied on the required performance for 300mm wafer transfer robot system.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.341-344
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• 2006

LED chips are produced by cutting the sapphire on which GaN is evaporated. To cut the sapphire wafer into each LED chip, at first the wafer is scribed by diamond tool. To get the sharp groove shape for the nice cutting plane it is important the diamond tool shape, load, etc when the wafer is scribed. Here we tried to simulate the scribing process and get the scribing condition to reduce the wear rate of diamond tool for the sharp groove shape.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.71-74
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• 2013

In this study, the effects of wafer warpage on the misalignment during wafer stacking process were investigated. The wafer with $45{\mu}m$ bow height warpage was purposely fabricated by depositing Cu thin film on a silicon wafer and the bonding misalignment after bonding was observed to range from $6{\mu}m$ to $15{\mu}m$. This misalignment could be explained by a combination of $5{\mu}m$ radial expansion and $10{\mu}m$ linear slip. The wafer warpage seemed to be responsible for the slip-induced misalignment instead of radial expansion misalignment.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.9
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• pp.831-835
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• 2000

The uniformity of themperature on a wafer is a wafer is one the most important parameters to conterol the RTF(Rapid Thermal Process) with proper input signals. It is impossible to achieve the uniformity of temperature without the exact estimation of temperature ar all points on the wafer. There fore, it is difficult to understand the internal dynamics as well as the structural complexities of the RTP, which is aprimary obstacle to measure the distributed temperatures on the wafer accurately. Furthermore, it is also hard to accomplish desirable estimation because only a few pyrometers are available in the general equipments. In the paper, a thermal model based on the chamber grometry of the AST SHS200 RTP system is developed to effectively control the thermal uniformity on the wafer. First of all, the estimation method of one-point measurement is developed, which is properly extended to the case of multi-point measurements. This thermal model is validated through simulation and experiments. The proposed work can be utilized to building a run-by -run or a real-time control of the RTP.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.4
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• pp.395-400
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• 2011

Scanning Probe Lithography is a method to localized oxidation on single crystal silicon wafer surface. This study demonstrates nanometer scale non contact lithography process on (100) silicon (p-type) wafer surface using AFM(Atomic force microscope) apparatuses and pulse controlling methods. AFM-based experimental apparatuses are connected the DC pulse generator that supplies ultra short pulses between conductive tip and single crystal silicon wafer surface maintaining constant humidity during processes. Then ultra short pulse durations are controlled according to various experimental conditions. Non contact lithography of using ultra short pulse induces electrochemical reaction between micro-scale tip and silicon wafer surface. Various growths of oxides can be created by ultra short pulse non contact lithography modification according to various pulse durations and applied constant humidity environment.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.1
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• pp.21-28
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• 2008

The final polishing process is based on slurry, pad, conditioner, equipment. Therefore, the concept of wafer final polishing is also necessary for repeatability of results between polished wafers. In this study, the machining conditions have a pressure, table speed, machining time and slurry ratio. This research investigated the surface characteristics that apply variable machining conditions and response surface methodology was used to obtain more flexible and optimumal condition base on Taguchi method. On the base of estimated response surface curvature from the equation and results of Taguchi method, combined design of experiment was considered to lead to optimumal condition. Finally, polished wafer was obtained mirror like surface.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.114-118
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• 2009

PVA (polyvinyl alcohol) brush cleaning method is a typical cleaning method for semiconductor cleaning process especially post-CMP cleaning. PVA brush contacts with the wafer surface and abrasive particle, generating the contact rotational torque of the brush, which is the removal mechanism. The brush rotational torque can overcome theoretically the adhesion force generated between the abrasive particle and wafer by zeta potential. However, after CMP (chemical mechanical polishing) process, many particles remained on the wafer because the brush was contaminated in previous post-CMP cleaning step. The abrasive particle on the brush redeposits to the wafer. The level of the brush contamination increased according to the cleaning run time. After cleaning the brush, the level of wafer contamination dramatically decreased. Therefore, the brush cleanliness effect on the cleaning performance and it is important for the brush to be maintained clearly.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2004.11a
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• pp.90-98
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• 2004

Nano/micro-scale studies on friction properties were conducted on Si (100) and three self-assembled monolayers (SAMs) (PFOTC, DMDM, DPDM) coated on Si-wafer by chemical vapor deposition technique. Experiments were conducted at ambient temperature $(24{\pm}1^{\circ}C)$ and humidity $(45{\pm}5\%)$. Nano-friction was evaluated using Atomic Force Microscopy (AFM) in the range of 0-40nN normal loads. In both Si-wafer and SAMs, friction increased linearly as a function of applied normal load. Results showed that friction was affected by the inherent adhesion in Si-wafer, and in the case of SAMs the physical/chemical structures had a major influence. Coefficient of friction of these test samples was also evaluated at the micro-scale using a micro-tribotester. It was observed that SAMs had superior frictional property due to their low interfacial energies. In order to study of the effect of contact area on friction coefficient at the micro-scale, friction was measured for Si-wafer and DPDM against Soda Lime balls (Duke Scientific Corporation) of different radii 0.25 mm, 0.5 mm and 1 mm at different applied normal loads $(1500,\;3000\;and\;4800{\mu}N)$. Results showed that Si-wafer had higher friction coefficient than DPDM. Furthermore, unlike that in the case of DPDM, friction was severely influenced by wear in the case of Si-wafer. SEM evidences showed that solid-solid adhesion to be the wear mechanism in Si-wafer.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.3
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• pp.289-294
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• 2012

There are several indicators to represent characteristics of chemical mechanical planarization (CMP) such as material removal rate (MRR), surface quality and removal uniformity on a wafer surface. Especially, the removal uniformity on the wafer edge is one of the most important issues since it gives a significant impact on the yield of chip production on a wafer. Non-uniform removal rate at the wafer edge (edge effect) is mainly induced by a non-uniform pressure from nonuniform pad curvature during CMP process, resulting in edge exclusion which means the region that cannot be made to a chip. For this reason, authors tried to minimize the edge exclusion by using an edge profile control (EPC) ring. The EPC ring is equipped on the polishing head with the wafer to protect a wafer from the edge effect. Experimental results showed that the EPC ring could dramatically minimize the edge exclusion of the wafer. This study shows a possibility to improve the yield of chip production without special design changes of the CMP equipment.

• Journal of ILASS-Korea
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• v.12 no.4
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• pp.185-190
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• 2007

There is a growing interest to develop a new cleaning technology to overcome the disadvantages of wet cleaning technologies such as environmental pollution and the cleaning difficulty of contaminants on integrated circuits. Laser cleaning is a potential technology to remove various pollutants on a wafer surface. However, there is no fundamental data about cleaning efficiencies and cleaning mechanisms of contaminants on a wafer surface using a laser cleaning technology. Therefore, the cleaning characteristics of a wafer surface using an excimer laser were investigated in this study. Fingerprint consisting of inorganic and organic materials was chosen as a representative of pollutants and the effectiveness of a laser irradiation on a wafer cleaning has been investigated qualitatively and quantitatively. The results have shown that cleaning degree is proportional to the laser irradiation time and repetition rate, and quantitative analysis conducted by an image processing method also have shown the same trend. Furthermore, the cleaning efficiency of a wafer contaminated by fingerprint strongly depended on a photothermal cleaning mechanism and the species were removed in order of hydrophilic and hydrophobic contaminants by laser irradiation.