• Journal of the Semiconductor & Display Technology
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• v.12 no.4
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• pp.39-44
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• 2013

In the semiconductor heat-treatment process, the temperature uniformity determines the film quality of a wafer. This film quality effects on the overall yield rate. The heat transfer of the wafer surface in the heat-treatment process equipment is occurred by convection and radiation complexly. Because of this, there is the nonlinearity between the wafer temperature and reactor. Therefore, the accurate prediction of temperature on the wafer surface is difficult without the direct measurement. The thermal camera and the T/C wafer are general ways to confirm the temperature uniformity on the heat-treatment process. As above ways have limit to measure the temperature in the precise domain under the micro-scale. In this study, we developed the thin film type temperature sensor using the MEMS technology to establish the system which can measure the temperature under the micro-scale. We combined the experiment and numerical analysis to verify and calibrate the system. Finally, we measured the temperature on the wafer surface on the semiconductor process using the developed system, and confirmed the temperature variation by comparison with the commercial T/C wafer.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2217-2220
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• 2007

In this paper, we propose a new wafer level package (WLP) for the RF MEMS applications. The Film Bulk Acoustic Resonator (FBAR) are fabricated and hermetically packaged in a new wafer level packaging process. With the use of Au-Sn eutectic bonding method, we bonded glass cap and FBAR device wafer which has groove-shaped via formed in the backside. The device wafer includes a electrical bonding pad and groove-shaped via for connecting to the external bonding pad on the device wafer backside and a peripheral pad placed around the perimeter of the device for bonding the glass wafer and device wafer. The glass cap prevents the device from being exposed and ensures excellent mechanical and environmental protection. The frequency characteristics show that the change of bandwidth and frequency shift before and after bonding is less than 0.5 MHz. Two packaged devices, Tx and Rx filters, are attached to a printed circuit board, wire bonded, and encapsulated in plastic to form the duplexer. We have designed and built a low-cost, high performance, duplexer based on the FBARs and presented the results of performance and reliability test.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.148-155
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• 2008

This study presents a process control of the wafer edge exposure (WEE) used in 300[mm] wafer environment. WEE, as a key module of the overall track system (coater and developer) for making patterns on wafer, is a system to expose the UV-ray on the wafer to remove a photo resist around edge of the wafer. It can measure, memorize and control the distance and angles from wafer center to edge. Recently in the 300[mm] semiconductor fabrication, the track system strongly requires that WEE station has a controller with high throughput and accuracy to increase process efficiency. We have designed and developed the controller, and present here a WEE control algorithm and experimental results.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.1-7
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• 2017

Multi-wafer planetary type chemical vapor deposition reactors are widely used in thin film growth and suitable for large scale production because of the high degree of growth rate uniformity and process reproducibility. In this study, a two-dimensional model for estimating the effect of the gap between satellite and wafer on the wafer surface temperature distribution is developed and analyzed using computational fluid dynamics technique. The simulation results are compared with the results obtained from an analytical method. The simulation results show that a drop in the temperature is noticed in the center of the wafer, the temperature difference between the center and wafer edges is about $5{\sim}7^{\circ}C$ for all different ranges of the gap, and the temperature of the wafer surface decreases when the size of the gap increases. The simulation results show a good agreement with the analytical ones which is based on one-dimensional heat conduction model.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.42-45
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• 2002

General wheel mark in mono-crystalline silicon wafer finding is able to be expected because it depends on radius ratio and angular velocity ratio of wafer and wheel. The pattern is predominantly determined by the contour of abrasive grits resulting from a relative motion. Although such a wheel mark is made uniform pattern if the process parameters are fixed, sub-surface defect is expected to be distributed non-uniformly because of characteristic of mono-crystalline silicon wafer that has diamond cubic crystal. Consequently it is considered that this phenomenon affects the following process. This paper focused on kinematic analysis of wafer grinding process and simulation program was developed to verify the effect of process variables on wheel mark. And finally, we were able to predict sub-surface defect distribution that considered characteristic of mono-crystalline silicon wafer

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.9
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• pp.2315-2328
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• 1993

The turbulence effect of particle deposition on a horizontal free-standing wafer in a vertical flow has been studied numerically by using the low-Reynolds-number k-.epsilon. turbulence model. For both the upper and lower surfaces of the wafer, predictions are made of the averaged particle deposition velocity and its radial distribution. Thus, it is now possible to obtain local information about the particle deposition on a free-standing wafer. The present result indicates that the particle deposition velocity on the lower surface of wafer is comparable to that on the upper one in the diffusion controlled deposition region in which the particle sizes are smaller than $0.1{\mu}m$. And it is found in this region that, compared to the laminar flow case, the averaged deposition velocity under the turbulent flow is about two times higher, and also that the local deposition velocity at the center of wafer is high equivalent to that the wafer edge.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.2
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• pp.310-317
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• 2013

In this paper, the contact pressure of the wafer and polishing pad for final polishing process for 300 mm-wafer were investigated through numerical analysis using FEM tool, ANSYS. The distribution of the contact pressure is one of main parameters which affects on the flatness and surface roughness of polished wafers. Two types of polishing head, a hard type head with ceramic disk and a soft type head with air bag were considered. The effects of the deformation and initial shape of table on the contact pressure were also examined. Both heads and tables were modeled as 3D finite element model from solid model, and the material properties of polishing pads and rubber plate for the air-bag head were obtained from tensile tests. The contact pressure deviation on wafer surface was smaller with air bag head than hard type head even when the table had form errors such as convex or concave. From this 3D analysis, it could be concluded that the air-bag head has better uniformity of the contact pressure on wafer. Also, the effects of inner diameter of air bag and radial clearance between wafer and retainer were investigated as view point of contact pressure concentration on the edge of wafer.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1508-1511
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• 1997

In this paper, design parameters of Rapid Thermal Processing(RrW) to minimize the wafer tempera ture uniformity errors are proposed. 1,anip ling positions and the wafer height are important parameters for waf er temperature uniformity in R'I'P. We propose the method to seek lamp ling positions and the wafer height for optimal temperature uniformity. l'he ~~roposed method is applied to seek optimal lamp ling positions and the waf er height of 8 inch wafer. 'I'o seek the optimal lamp ling positions and the wafer height, we var\ulcorner. lamp ling 110s itions and the wafer height and then formulate the wafer temperature uniformity problem to the linear programmi ng problem. Finally, it is shown that the wafer temperature uniformity in RI'I' designed by optimal prarneters is improved to comparing with Ii'l'P designed by the other method.

• Particle and aerosol research
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• v.5 no.1
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• pp.17-27
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• 2009

Particle deposition on a semiconductor wafer larger than 100 mm was studied experimentally and numerically. Particularly the electrostatic effect on particle deposition velocity was investigated. The experimental apparatus consisted of a particle generation system, a particle deposition chamber and a wafer surface scanner. Experimental data of particle deposition velocity were obtained for a semiconductor wafer of 200 mm diameter with the applied voltage of 5,000 V and PSL particles of the sizes between 83 and 495 nm. The experimental data of particle deposition velocity were compared with the present numerical results and the existing experimental data for a 100 mm wafer by Ye et al. (1991) and Opiolka et al. (1994). The present numerical method took into consideration the particle transport mechanisms of convection, Brownian diffusion, gravitational settling and electrostatic attraction in an Eulerian frame of reference. Based on the comparison of the present experimental and numerical results with the existing experimental results the present experimental method for a 200 mm semiconductor wafer was found to be able to present reasonable data.