• Journal of the Korea Society for Simulation
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• v.18 no.4
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• pp.219-225
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• 2009

The primary purpose of this study is to build computer models referring overall flow of complex and various semiconductor wafer manufacturing process and to implement a educational model which operates with a presentation tool showing device design. It is important that Korean semiconductor industries secure high competitive power on efficient manufacturing management and to develop technology continuously. Models representing the FAB processes and the functions of each process are developed for Seoul National University Semiconductor Research Center. However, it is expected that the models are effective as visually educational tools in Korean semiconductor industries. In addition, it is anticipated that these models are useful for semiconductor process courses in academia. Scalability and flexibility allow semiconductor manufacturers to customize the models and perform simulation education. Subsequently, manufacturers save budget.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.3
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• pp.233-240
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• 2023

p-type Tunnel Oxide Passivating Contacts (TOPCon) solar cell is fabricated with a poly-Si/SiO_x structure. It simultaneously achieves surface passivation and enhances the carriers' selective collection, which is a promising technology for conventional solar cells. The quality of passivation is depended on the quality of the tunnel oxide layer at the interface with the c-Si wafer, which is affected by the bond of SiO formed during the subsequent annealing process. The highest cell efficiency reported to date for the laboratory scale has increased to 26.1%, fabricated by the Institute for Solar Energy Research. The cells used a p-type float zone silicon with an interdigitated back contact (IBC) structure that fabricates poly-Si and SiO_x layer achieves the highest implied open-circuit voltage (iV_oc) is 750 mV, and the highest level of edge passivation is 40%. This review presents an overview of p-type TOPCon technologies, including the ultra-thin silicon oxide layer (SiO_x) and poly-silicon layer (poly-Si), as well as the advancement of the SiO_x and poly-Si layers. Subsequently, the limitations of improving efficiency are discussed in detail. Consequently, it is expected to provide a basis for the simplification of industrial mass production.

• Journal of Convergence Korean Medicine
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• v.2 no.1
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• pp.5-12
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• 2021

Objectives: The purpose of this study is to fabricate an ultra-fine ginsenoside particle atomizer that can provide a new treatment method by delivering ginsenoside components that have a therapeutic effect on respiratory diseases directly to the lungs. Methods: We fabricated the AAO vibrating mesh by using the micromachining process. The starting substrate of an AAO wafer has a 350nm pore diameter with 50㎛ thickness. A photomask having several 5㎛ opening holes with a 100㎛ pitch was used to separate each nanopore nozzle. The photoresist structure was optimized to pattern the nozzle area during the lift-off process precisely. The commercial vibrating mesh was removed from OMRON's NE-U100 product, and the fabricated AAO vibrating mesh was installed. A diluted sample of 20mL with 30% red ginseng concentrate was prepared to atomize from the device. Results: As a result of liquid chromatography analysis before spraying the ginsenoside solution, ginsenoside components such as 20S-Rg3, 20R-Rg3, and Rg5 were detected. After spraying through the AAO vibrating mesh, ginsenosides of the same component could be detected. Conclusion: A nutrient solution containing ginsenosides was successfully sprayed through the AAO vibrating mesh with 350 nm selective pores. In particular, during the atomizing experiment of ginsenoside drug solution having excellent efficacy in respiratory diseases, it was confirmed that atomizing through the AAO vibrating mesh while maintaining most of the active ingredients was carried out.

• Tribology and Lubricants
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• v.40 no.2
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• pp.47-53
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• 2024

Surface topography plays a decisive role in determining the performance of several precision components. In particular, the surface roughness of semiconductor devices affects the precision of the circuit. In this regard, the surface topography of a given surface needs to be appropriately assessed. Typically, the average roughness is used as one of the main indicators of surface finish quality because it is influenced by both dynamic and static parameters. Owing to the increasing demand for such accurate and reliable surface measurement systems, studies are continuously being conducted to understand the parameters of surface roughness and measure the average roughness with high reliability. However, the differences in the measurement methods of surface roughness are not clearly understood. Hence, in this study, the surface roughness of the back of a silicon wafer was measured using both contact and noncontact methods. Subsequently, a comparative analysis was conducted according to various surface roughness parameters to identify the differences in surface roughness depending on the measurement method. When using a 3D laser confocal microscope, even smaller surface asperities can be measured compared with the use of a 3D profiler. The results are expected to improve the understanding of the surface roughness characteristics of precision components and be used as a useful guideline for selecting the measurement method for surface topography assessment.

• Journal of Oral Medicine and Pain
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• v.30 no.4
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• pp.411-426
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• 2005

The purpose of this study was to investigate the effects of occlusal condition and clenching level on the mandibular torque rotational movement. For this study, healthy 14 men without any symptoms and signs of temporomandibular disorders were selected. Mandibular torque rotational movement was observed in each circumstance of combination of three occlusal conditions such as natural dentition, with wafer of 3.6 mm thickness, and wafer with resin stop of 14 mm thickness total during hard biting of bite stick at maximum voluntary contraction(MVC) and 50% of MVC level of surface EMG activity of masseter muscle. Electromyographic activity and mandibular torque rotational movement were observed using BioEMG and BioEGN in $BioPak^{(R)}$ system. Each biting movement in each circumstance was composed of clenching one time and hard biting of wooden stick two times. The observed items were opening distance, velocity and amount of torque rotational movement in mandibular movement, and the data were statistically processed with $SPSS^{(R)}$ windows (ver.10.0). The results of this study were as follows: 1. There were no differences in the mandibular movement distance between those value in both biting sides, and between those in both clenching forces, but the mandibular velocity showed a different results by clenching force. For the amount of torque rotational movement, there were no difference in the value of the frontal plane but some significant difference was in the value of the horizontal plane by biting side. 2. The mandibular movement distance and the mandibular velocity in both planes were higher by maximum voluntary contraction than those by half maximum voluntary contraction, and amount of torque rotational movement in the horizontal plane was also increased by maximum voluntary contraction. 3. The opening distance in both planes were decreased with the increase of vertical dimension of occlusion, namely, by the occlusal appliances, and this pattern was also showed in the mandibular velocity in case of hard biting by maximum voluntary contraction. However, the amount of torque rotational movement were not different by the increase of vertical dimension of occlusion. 4. The value of angle and distance of the torque rotational movement in the hard biting of wooden stick were generally higher than those in the clenching without wooden stick in both planes without regard to occlusal conditions and/or clenching forces.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.173-173
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• 2010

Recently, a patterned sapphire substrate (PSS) has been intensively used as one of the effective ways to reduce the dislocation density for the III-nitride epitaxial layers aiming for the application of high-performance, especially high-brightness, light-emitting diodes (LEDs). In this paper, we analyze the growth kinetics of the atoms and crystalline quality for the undopped-GaN depending on the facets of the pattern fabricated on a sapphire substrate. The effects of the PSS on the device characteristics of InGaN/GaN LEDs were also investigated. Several GaN samples were grown on the PSS under the different growth conditions. And the undoped-GaN layer was grown on a planar sapphire substrate as a reference. For the (002) plane of the undoped-GaN layer, as an example, the line-width broadening of the x-ray diffraction (XRD) spectrum on a planar sapphire substrate is 216.0 arcsec which is significantly narrower than that of 277.2 arcsec for the PSS. However, the line-width broadening for the (102) plane on the planar sapphire substrate (363.6 arcsec) is larger than that for the PSS (309.6 arcsec). Even though the growth parameters such as growth temperature, growth time, and pressure were systematically changed, this kind of trend in the line-width broadening of XRD spectrum was similar. The emission wavelength of the undoped-GaN layer on the PSS was red-shifted by 5.7 nm from that of the conventional LEDs (364.1 nm) under the same growth conditions. In addition, the intensity for the GaN layer on the PSS was three times larger than that of the planar case. The spatial variation in the emission wavelength of the undoped-GaN layer on the PSS was statistically ${\pm}0.5\;nm$ obtained from the photoluminescence mapping results throughout the whole wafer. These results will be discussed in terms of the mixed dislocation depending on the facets and the period of the patterns.

• Korean Journal of Materials Research
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• v.5 no.6
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• pp.690-698
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• 1995

The Poly-S $i_{1-x}$G $e_{x}$ thin films were deposited on oxidized Si wafer by RTCVD(rapid thermal chemical vapor deposition) using Si $H_4$and Ge $H_4$, at 450 ~5$50^{\circ}C$. The variation of Ge mole fraction and the deposition rate of S $i_{1-x}$G $e_{x}$ thin film were studied as a function of the deposition temperature and the Ge $H_4$/Si $H_4$input ratio, and the crystal phase and the surface roughness were studied by XRD and AFM(atomic force microscopy), respectively. The experimental results showed that the activation energy for the deposition of poly-S $i_{1-x}$G $e_{x}$ was about 32~37Kca /mol and the deposition rate of S $i_{1-x}$G $e_{x}$ thin films was increased with increasing the deposition temperature and the input ratio. From the analysis of composition, it was known that the Ge mole fraction within the poly-S $i_{1-x}$G $e_{x}$ thin film was decreased with decreasing the input ratio and increasing the deposition temperature. As-deposited S $i_{1-x}$G $e_{x}$ thin films were polycrystalline over the entire experimental range. But those were amorphous at the deposition temperature of 450, 475$^{\circ}C$ and the input ratio of 0.05. By adding the Ge $H_4$, poly-S $i_{1-x}$G $e_{x}$ thin film were deposited at relatively lower deposition temperatures($\leq$ 5$50^{\circ}C$) than those of conventional poly-Si(>$600^{\circ}C$). From surface roughness measurement of poly-S $i_{1-x}$G $e_{x}$ it was found that the surface roughness( $R_{i}$ ) increased with increasing the deposition temperature and input ratio.and input ratio.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.16 no.3
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• pp.116-120
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• 2006

We have investigated plasma spray coated $Al_2O_3$ layers on Al-60 series substrates for development of wafer electrostatic chuck in semiconductor dry etching system. Samples were prepared without/with cooling bar on backside of samples, at various distances, and with different powder feed rates. There were many cracks and pores in the $Al_2O_3$ layers coated on Al-60 series substrates without cooling bar on the backside of samples. But the cracks and pores were almost disappeared in the $Al_2O_3$ layers on Al-60 series substrates coated with cooling bar on the back side of samples, 15 g/min. powder feed rate and various 60, 70, 80 mm working distances. Then the surface morphology was not changed with various working distances of 60, 70, 80 mm. When the powder feed rate was changed from 15 g/min to 20 g/min, the crack did not appear, but few pores appeared. Also the $Al_2O_3$ layer was coated with many small splats compared with $Al_2O_3$ layer coated with 15 g/min powder feed rate. The deposited rate of $Al_2O_3$ layer was higher when the process was done without cooling bar on the back side of sample than that with cooling bar on the back side of sample.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.