• Proceedings of the KSME Conference
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• 2000.11b
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• pp.261-266
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• 2000

Temperature variation during silicon wafer baking is mainly due to natural convection caused by temperature difference between silicon wafer and upper plate. Several cases are tested and calculated numerically to improve temperature uniformity. The temperature difference and velocity magnitude in the flow cell is reduced for a small gap between the wafer and upper plate because the natural convection force is suppressed in the small space. The uniform temperature distribution can be obtained with controling the incoming flow distribution from the upper plate. An alternative method is the adiabatic wall condition on the upper plate to maintain the temperature uniformity within $0.3^{\circ}C$ on the water plate.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.05a
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• pp.743-746
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• 2000

The removal of contaminants of silicon wafers has been investigated by various methods. Laser cleaning is the new dry cleaning technique to replace wafer wet cleaning in the near future. A dry laser cleaning uses inert gas jet to remove contaminant particles lifted off by the action of a KrF excimer laser. A laser cleaning model is developed to simulate the cleaning process and analyze the influence of contaminant particles and experimental parameters on laser cleaning efficiency. The model demonstrates that various types of submicrometer-sized particles from the front sides of silicon wafer can be efficiently removed by laser cleaning. The laser cleaning is explained by a particle adhesion model. including van der Waals forces and hydrogen bonding, and a particle removal model involving rapid thermal expansion of the substrate due to the thermoelastic effect. In addition, the experiment of wafer laser cleaning using KrF excimer laser was conducted to remove various contaminant particles.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.05a
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• pp.854-857
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• 2000

Chemical Mechanical Polishing(CMP) has been accepted as one of the essential processes for VLSI fabrication. However, as the polishing process continues, pad pores get to be glazed by polishing residues, which hinder the supply of new slurry. This defect makes removal rate decrease with a number of polished wafer and the desired within-chip planarity, within wafer and wafer-to-wafer nonuniformity are unable to be achieved. So, pad conditioning is essential to overcome this defect. The eletroplated diamond grit disk is used as the conventional conditioner, And alumina long fiber, the .jet power of high pressure deionized water and vacuum compression are under investigation. But, these methods have the defects like scratches on wafer surface by out of diamond grits, subsidences of pad pores by over-conditioning, and the limits of conditioning effect. To improve these conditioning methods. this paper presents the Characteristics of Ultrasonic conditioning aided by cavitation.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.5
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• pp.350-355
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• 2000

The fabrication of sapphire wafer in C plane has been developed by horizontal Bridgeman method and GaN based semiconductor epitaxial growth has been carried out in metal organic chemical vapour deposition. The single crystalline ingot of sapphire has been utilized for 2 inch sapphire wafers and wafer slicing and lapping machines were designed. These several steps of lapping processes provided the mirror-like surface of sapphire wafer. The measurements of the surface flatness and the roughness were carried out by the atomic force microscope. The GaN thin film growth on the developed wafer was confirmed the wafer quality and applicability to blue light emitting devices.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.16-21
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• 2020

How accurately reproducible energy is delivered to the wafer in the process of making thin films using PE-CVD (Plasma enhanced chemical vapor deposition) during the semiconductor process. This is the most important technique, and most of the reaction on the wafer surface is made by thermal energy. In this study, we studied the method of monitoring the change of thermal energy transferred to the wafer surface by monitoring the temperature change according to the change of the thin film formed on the showerhead facing the wafer. Through this research, we could confirm the monitoring of wafer thin-film which is changed due to abnormal operation and accumulation of equipment, and we can expect improvement of semiconductor quality and yield through process reproducibility and equipment status by real-time monitoring of problem of deposition process equipment performance.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.55-59
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• 2024

Plasma Enhanced Chemical Vapor Deposition (PE-CVD) is a widely used technology in semiconductor manufacturing for thin film deposition. The implementation of wafer guide rings in PE-CVD processes is crucial for enhancing efficiency and product quality by ensuring uniform deposition around wafer edges and reducing particle generation. On the other hand, to prevent overall temperature non-uniformity and degradation of thin film quality within the chamber, it is essential to consider various parameters comprehensively. In this study, after applying the wafer guide rings, temperature variations and fluid flow changes were simulated. Additionally, by simulating the temperature and flow changes when applied to the PE-CVD chamber, this paper discusses the importance of optimizing variables within the entire chamber.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.1033-1034
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• 2010

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.509-510
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• 2010