• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.349-357
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• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.123-126
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• 2004

Demands on dealing with multimedia data through the network have been increased, and networking multimedia devices require processing, transmitting , and receiving the digital data. In order to implement the network for high performance and low cost, we may have to integrate the dedicated hardware into a system on a chip by spending an extra amount of silicon resource. In this paper, we describe hardware implementation of TCP/IP protocol stack which is now popular to connect multiple PCs and peripherals by means of networks. For evaluation we used ALTERA APEX 20K600EBC652 FPGA with 600,000 gates. The operating frequency is estimated 29.9MHz and it used area of $26\%$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• 한국정보과학회 언어공학연구회:학술대회논문집(한글 및 한국어 정보처리)
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• 한국정보과학회언어공학연구회 1991년도 제3회 한글 및 한국어정보처리 학술대회
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• pp.287-299
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• 1991

본 논문은 하드웨어 구현이 가능한 신경 회로망을 구성하여 한글 문자 인식을 수행하였다. 먼저 입력 장치로부터 받아들인 문자 영상은 인식 속도를 높히기 위하여 특별한 전처리 과정 없이 직접 피쳐를 추출하였으며 추출한 피쳐로는 하드웨어 구현이 용이한 교차 피쳐와 투영 피쳐를 이진화로 코딩하였다. 신경 회로망의 하드웨어 구현을 가능하게 하기위해서 정수형 연결 강도와 비선형 Hard-limit 함수를 가지고 학습을 하는 Rounding 학습 방법을 도입하여 학습시켰으며 한글의 구조적 특성을 이용하여 한글을 유형별로 Module화 및 Submodule화 작업을 수행한 다음 인식하는 계층적인 문자 인식 시스템을 구성하였다. 그리고 이러한 방법을 이용하여 한글 문자 인식용 CMOS 신경회로망 Chip을 설계하였다.

• 한국정보통신학회논문지
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• 제9권6호
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• pp.1211-1217
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• 2005

Embedded system은 소수의 System-On-Chip (SOC)으로 대부분의 기능이 구현되어지는 추세이며, 이러한 SOC의 구조는 대체로 RISC 기반의 내장 마이크로프로세서를 중심으로 발전해 왔다. 하지만 RISC 기반의 ARM, MIPS등의 범용 프로세서들은 점차 그 필요성이 커지고 있는 네트워크 기능과 멀티미디어 처리 기능 등에 대해서는 많은 고려 없이 설계된 프로세서들이다. 소규모 사업자 및 개인 사용자를 위한 네트워크 기기의 경우는 가격대비 성능이 우수한 제품이 시장을 차지하는데 유리하므로, 지금까지 대부분의 경우에서 전용 하드웨어를 사용하지 않고, PHY와 MAC layer 일부의 기본적인 기능을 제외한 나머지 네트워크 기능을 모두 상기한 내장 마이크로프로세서로 처리하고 있다. VDSL, FTTH과 같이 고속 인터넷을 가능하게 하는 기술이 발전함에 따라, 기존의 범용 프로세서에 기반을 둔 네트워크 기기는 빠른 속도로 그 성능의 한계에 다다르고 있다. 이는 단순히 프로세서의 동작 속도를 높이는 것으로 해결할 수 있는 문제가 아닌 것으로 보이며, 네트워크 프로토콜의 처리에 최적화 되어 있지 않은 범용 프로세서의 사용에 근본적인 문제점이 있다고 하겠다. 본 연구를 통하여 네트워크 기능 수행에 효율적인 네트워크 프로세서를 설계하고 이를 Home gateway용 SOC에 내장하고 성능을 측정하여 그 상용화 가능성을 타진한다.

• Smart Structures and Systems
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• 제6권5_6호
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• pp.579-593
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• 2010

Low-power radio frequency (RF) chip transceiver technology and the associated structural health monitoring platforms have matured recently to enable high-rate, lossless transmission of measurement data across large-scale sensor networks. The intrinsic value of these advanced capabilities is the allowance for high-quality, rapid operational modal analysis of in-service structures using distributed accelerometers to experimentally characterize the dynamic response. From the analysis afforded through these dynamic data sets, structural identification techniques can then be utilized to develop a well calibrated finite element (FE) model of the structure for baseline development, extended analytical structural evaluation, and load response assessment. This paper presents a case study in which operational modal analysis is performed on a three-span prestressed reinforced concrete bridge using a wireless sensor network. The low-power wireless platform deployed supported a high-rate, lossless transmission protocol enabling real-time remote acquisition of the vibration response as recorded by twenty-nine accelerometers at a 256 Sps sampling rate. Several instrumentation layouts were utilized to assess the global multi-span response using a stationary sensor array as well as the spatially refined response of a single span using roving sensors and reference-based techniques. Subsequent structural identification using FE modeling and iterative updating through comparison with the experimental analysis is then documented to demonstrate the inherent value in dynamic response measurement across structural systems using high-rate wireless sensor networks.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1897-1900
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• 2004

In recent years, a lot of industrial equipments have serial communication channel such as FieldBus (CAN, Profibus, etc.) or Ethernet that provides real time communication between industrial equipments. Theses applications include gantry crane, robot, chip mounter, etc.. In this paper, we discuss the synchronization technique for networked multi-motor systems where controllers (commercial servo amps) are distributed and interconnected by CAN (Controller Area Networks). We first describe the equivalent model for the individual servo-amp and motor using the frequency response. We design the $H{\infty}$ controller for motion synchronization. Finally, the synchronization technique using the equivalent model and the $H{\infty}$ controller is verified by the simulation and the experiment.

• 전기학회논문지P
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• 제64권4호
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• pp.321-326
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• 2015

Smart metering is one of the most implementable internet-of-thing service. In order to implement the smart metering, a wireless communication network should be newly designed and evaluated so as to satisfy quality-of-service of smart metering. In this paper, we consider a wireless network for the smart metering implemented with multi-purpose wireless chips and channel coding-functioned micro controllers. Especially, channel coding is newly adopted to improve successful frame transmission probability. Based on the successful frame transmission probability, average transmission delay and delay violation probability are analyzed. Using the analytical results, service coverage expansion is evaluated. Through the delay analysis, service feasibility can be verified. According to our results, channel coding needs not to be utilized to improve the delay performance if the smart metering service coverage is several tens of meters. However, if more coverage is required, chanel coding adoption definitely reduces the delay time and improve the service feasibility.

• Journal of Computing Science and Engineering
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• 제6권4호
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• pp.257-266
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• 2012

This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.451-458
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• 2013

This paper describes a design of LIN MCU using efficient memory accessing architecture which provides concurrent data and address fetch for faster communication. By using slew rate control it can reduce EMI emission while satisfying required communication specifications. To verify the efficiency of the LIN MCU, we developed a SoC and tested for several data packets. Measurements show that this LIN MCU improves network efficiency up to 17.19 % and response time up to 31.26 % for nominal cases. EMI radiation also can be reduced up to 10 dB.