• Journal of Biomedical Engineering Research
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• v.30 no.2
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• pp.103-112
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• 2009

Neuron-on-a-Chip technology is based on advanced neuronal culture technique, surface micropatterning, microelectrode array technology, and multi-dimensional data analysis techniques. The combination of these techniques allowed us to design and analyze live biological neural networks in vitro using real neurons. In this review article, two underlying technologies are reviewed: Microelectrode array technology and Neuronal patterning technology. There are new opportunities in the fusion of these technologies to apply them in neurobiology, neuroscience, neural prostheses, and cell-based biosensor areas.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.186-192
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• 1996

A modified learning rule is introduced for the implementation of feedforward artificial neural networks with on-chip learning circuitry using standard analog CMOS technology. Learning rule, is modified form the EBP (error back propagation) rule which is one of the well-known learning rules for the feedforward rtificial neural nets(FANNs). The employed MEBP ( modified EBP) rule is well - suited for the hardware implementation of FANNs with on-chip learning rule. As a ynapse circuit, a four-quadrant vector-product linear multiplier is employed, whose input/output signals are given with voltage units. Two $2{\times}2{\times}1$ FANNs are implemented with the learning circuitry. The implemented FANN circuits have been simulatied with learning test patterns using the PSPICE circuit simulator and their results show correct learning functions.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.309-312
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• 2001

A primitive gas classification system which can classify limited species of gas was designed and simulated. The 'electronic nose' consists of an array of 4 metal oxide gas sensors with different selectivity patterns, signal collecting unit and a signal pattern recognition and decision Part in PLD(programmable logic device) chip. Sensor array consists of four commercial, tin oxide based, semiconductor type gas sensors. BP(back propagation) neutral networks with MLP(Multilayer Perceptron) structure was designed and implemented on CPLD of fifty thousand gate level chip by VHDL language for processing the input signals from 4 gas sensors and qualification of gases in air. The network contained four input units, one hidden layer with 4 neurons and output with 4 regular neurons. The 'electronic nose' system was successfully classified 4 kinds of industrial gases in computer simulation.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.169-175
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• 2014

NG-SDH system is connected with networks throughout optical fibers. Network synchronization controller is a necessary for the data synchronization in each optical transmission system. In this paper, we have design and implementation the network synchronization controller using SOPC(system on a programmable chip) design technic. For this network synchronization controller we use FPGA in Altera. FPGA includes 32bit CPU, DPRAM(dual port ram), digital input/output port, transmitter and receiver framer, phase difference detector. We also confirm that designed network synchronization controller satisfies the ITU-T G.813 timing requirements.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.9-15
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• 2006

This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.

• Journal of applied mathematics & informatics
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• v.28 no.1_2
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• pp.539-551
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• 2010

Low scalability and power efficiency of the shared bus in SoCs is a motivation to use on chip networks instead of traditional buses. In this paper we have modified the Orion power model to reach an analytical model to estimate the average message energy in K-Ary n-Cubes with focus on the number of virtual channels. Afterward by using the power model and also the performance model proposed in [11] the effect of number of virtual channels on Energy-Delay product have been analyzed. In addition a cycle accurate power and performance simulator have been implemented in VHDL to verify the results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.647-655
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• 2003

Commonly used SAW duplexers have a difficulty on manufacture so that a transmission line is printed on the package or an LTCC multi-layer is needed because a quarter-wave transmission line which is a kind of an isolation network is applied to the SAW duplexers. In this study, new structures of one chip type SAW duplexers are proposed. In the proposed structure, Tx and Rx SAW ladder filters and isolation networks are located on a single 36LiTaO$_3$ piezoelectric substrate. The manufacture process is very simple than commonly used product. It is possible to improve tile performance by means of optimizing the micro-strip line lumped elements. It is easy to integrate and modulate with other surrounding components. The optimal design techniques can be applied to other kind of multi-port devices.

• Journal of computational fluids engineering
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• v.14 no.4
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• pp.86-92
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• 2009

Nowadays, the development of microfluidic chip [i.e. biochip, micro-total analysis system ($\mu$-TAS) and LOC (lab-on-a-chip)] becomes more active, and the microchannels to deliver fluid by pressure or electroosmotic forces tend to be more complex like electronic circuits or networks. For a simple network of channels, we may calculate the pressure and the flow rate easily by using suitable formula. However, for complex network it is not handy to obtain such information with that simple way. For this reason, Graphic User Interface (GUI) program which can rapidly give required information should be necessary for microchip designers. In this paper, we present a GUI program developed in our laboratory and the simple theoretical formula used in the program. We applied our program to simple case and could get results compared well with other numerical results. Further, we applied our program to several complex cases and obtained reasonable results.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.9
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• pp.3515-3538
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• 2015

Data accuracy can be increased by detecting and removing the incorrect data generated in wireless sensor networks. By increasing the data accuracy, network lifetime can be increased parallel. Network lifetime or operational time is the time during which WSN is able to fulfill its tasks by using microcontroller with on-chip memory radio transceivers, albeit distributed sensor nodes send summary of their data to their cluster heads, which reduce energy consumption gradually. In this paper a powerful algorithm using proactive fuzzy system is proposed and it is a mixture of fuzzy logic with comparative correlation techniques that ensure high data accuracy by detecting incorrect data in distributed wireless sensor networks. This proposed system is implemented in two phases there, the first phase creates input space partitioning by using robust fuzzy c means clustering and the second phase detects incorrect data and removes it completely. Experimental result makes transparent of combined correlated fuzzy system (CCFS) which detects faulty readings with greater accuracy (99.21%) than the existing one (98.33%) along with low false alarm rate.

• Journal of Communications and Networks
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• v.11 no.1
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• pp.1-10
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• 2009

In this paper, we propose a chip-level detection and a spectral-slice scheme for the tunable-transmitter/fixed-receiver (TTFR)-based asynchronous spectral phase-encoded optical codedivision multiple-access (CDMA) system combined with timeencoding. The chip-level detection can enhance the tolerance of multiple access interference (MAI) because the channel collision does not occur as long as there is at least one weighted position without MAI. Moreover, the spectral-slice scheme can reduce the interference probability because the MAI with the different frequency has no adverse effects on the channel collision rate. As a result, these techniques mitigate channel collisions. We analyze the channel collision rate theoretically, and show that the proposed system can achieve a lower channel collision rate in comparison to both conventional systems with and without the time-encoding method.