• 제목/요약/키워드: On/off current ratio

검색결과 358건 처리시간 0.03초

High Performance Current-Mode DC-DC Boost Converter in BiCMOS Integrated Circuits

  • Lee, Chan-Soo;Kim, Eui-Jin;Gendensuren, Munkhsuld;Kim, Nam-Soo;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
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    • 제12권6호
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    • pp.262-266
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    • 2011
  • A simulation study of a current-mode direct current (DC)-DC boost converter is presented in this paper. This converter, with a fully-integrated power module, is implemented by using bipolar complementary metal-oxide semiconductor (BiCMOS) technology. The current-sensing circuit has an op-amp to achieve high accuracy. With the sense metal-oxide semiconductor field-effect transistor (MOSFET) in the current sensor, the sensed inductor current with the internal ramp signal can be used for feedback control. In addition, BiCMOS technology is applied to the converter, for accurate current sensing and low power consumption. The DC-DC converter is designed with a standard 0.35 ${\mu}m$ BiCMOS process. The off-chip inductor-capacitor (LC) filter is operated with an inductance of 1 mH and a capacitance of 12.5 nF. Simulation results show the high performance of the current-sensing circuit and the validity of the BiCMOS converter. The output voltage is found to be 4.1 V with a ripple ratio of 1.5% at the duty ratio of 0.3. The sensing current is measured to be within 1 mA and follows to fit the order of the aspect ratio, between sensing and power FET.

플라즈마 CVD에 의한 고전압 비정질 실리콘 박막 트랜지스터의 제작 (Fabrication of High Voltage a-Si:H TFT Plasma Chemical Vapor Deposition)

  • Lee, Woo-Sun;Kang, Young-Chul;Kim, Hyung-Gon
    • 대한전기학회논문지
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    • 제43권2호
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    • pp.312-317
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    • 1994
  • We studied the fabrication and electrical characteristics of high voltage hydrogenerated amorphous silicon thin film transistor using plasma enchanced chemical vapor deposition(PECVD). The device shows 2500${\AA}$ SiOS12T, 400-1500${\AA}$ a-Si tickness, 350V output voltage and 9.55${\times}$10S04T average on/off current ratio. We found that the leakage current of high voltage TFT occurred 0-70V drain voltage. As the leakage current depend on the a-Si thickness, the leakage current of high voltage TFT decreased by reduction of the a-Si thickness.

Erbium 실리사이드를 이용하여 제작한 n-형 쇼트키장벽 관통트랜지스터의 전기적 특성 (Characteristics of Erbium silicided n-type Schottky barrier tunnel transistors)

  • Moongyu Jang;Kicheon Kang;Sunglyul Maeng;Wonju Cho;Lee, Seongjae;Park, Kyoungwan
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.779-782
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    • 2003
  • The theoretical and experimental current-voltage characteristics of Erbium silicided n-type Schottky barrier tunneling transistors (SBTTs) are discussed. The theoretical drain current to drain voltage characteristics show good correspondence and the extracted Schottky barrier height is 0.24 eV. The experimentally manufactured n-type SBTTs with 60 nm gate lengths show typical transistor behaviors in drain current to drain voltage characteristics. The drain current on/off ratio is about 10$^{5}$ at low drain voltage regime in drain current to gate voltage characteristics.

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Flexible 디스플레이로의 응용을 위한 플라스틱 기판 위의 박막트랜지스터의 제조 (Fabrication of thin Film Transistor on Plastic Substrate for Application to Flexible Display)

  • 배성찬;오순택;최시영
    • 대한전자공학회논문지SD
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    • 제40권7호
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    • pp.481-485
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    • 2003
  • 25㎛ 두께의 폴리이미드 박핀 기판을 glass 기판에 부착하여 최대 온도 150℃에서 비정질 실리콘 TFT를 제작하였다. 본 논문은 plastic 기판 위에 TFT가 제작되는 공정 절차를 요약하고 glass 위에 제작된 TFT와 ON/OFF 전달특성과 전계효과 이동도를 서로 비교해 보았다. a-SiN:H 코팅층은 plastic 기판의 표면 거칠기를 감소시키는 중요한 역할을 하여 TFT의 누설전류를 감소시키고 전계효과 이동도를 증가시켰다. 따라서 a-SiN:H 코팅층을 이용하여 plastic 기판에 양철의 TFT를 제작하였다.

PVA 배열층을 이용한 펜타신 유기 박막 트랜지스터의 전기적 특성 (An Electrical Characteristics on the Pentacene-Based Organic Thin-Film Transistors using PVA Alignment Layer)

  • 전현성;오환술
    • 한국전기전자재료학회논문지
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    • 제23권3호
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    • pp.177-182
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    • 2010
  • The pentacene-based organic thin film transistors(OTFTs) using polyvinylalcohol(PVA) alignment layer were fabricated on the $SiO_2$ evaporated to n-type (111) Si substrates. The pentacene film was deposited by thermally evaporated at $10^{-7}$ torr. X-ray diffraction (XRD) and atomic force microscope(AFM) measurement showed pentacene film which deposited on rubbed PVA layers were partially crystallized at (001) plane. The pentacene OTFTs with PVA layers rubbed perpendicular to the direction of current flow was shown to align better orientation than parallel rubbed case and thus to enhance the mobility and saturation current by a factor of 2.3 respectively. We obtained mobility by 0.026 $cm^2$/Vs and on-off current ratio by ${\sim}10^8$.

MIT characteristic of VO2 thin film deposited by ALD using vanadium oxytriisopropoxide precursor and H2O reactant

  • Shin, Changhee;Lee, Namgue;Choi, Hyeongsu;Park, Hyunwoo;Jung, Chanwon;Song, Seokhwi;Yuk, Hyunwoo;Kim, Youngjoon;Kim, Jong-Woo;Kim, Keunsik;Choi, Youngtae;Seo, Hyungtak;Jeon, Hyeongtag
    • Journal of Ceramic Processing Research
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    • 제20권5호
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    • pp.484-489
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    • 2019
  • VO2 is an attractive candidate as a transition metal oxide switching material as a selection device for reduction of sneak-path current. We demonstrate deposition of nanoscale VO2 thin films via thermal atomic layer deposition (ALD) with H2O reactant. Using this method, we demonstrate VO2 thin films with high-quality characteristics, including crystallinity, reproducibility using X-ray diffraction, and X-ray photoelectron spectroscopy measurement. We also present a method that can increase uniformity and thin film quality by splitting the pulse cycle into two using scanning electron microscope measurement. We demonstrate an ON / OFF ratio of about 40, which is caused by metal insulator transition (MIT) of VO2 thin film. ALD-deposited VO2 films with high film uniformity can be applied to next-generation nonvolatile memory devices with high density due to their metal-insulator transition characteristic with high current density, fast switching speed, and high ON / OFF ratio.

Effect of Hafnium Oxide on ALD Grown ZnO Thin Film Transistor

  • Choi, Woon-Seop
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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    • pp.211-213
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    • 2008
  • The TFTs from ZnO semiconductor with hafnium oxide dielectrics were prepared by atomic layer deposition to characterize the electrical properties. Good electrical properties of oxide TFT was obtained with channel mobility of $2.1\;cm^2/Vs$, threshold voltage of 0 V, the subthreshold slope of 0.9 V/dec, and on to off current ratio of $10^6$.

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CMOS Inverter Design based on Double Gate Ultra-Thin Body MOSFETs

  • Park, Sang Chun;Ahn, Yongsoo
    • EDISON SW 활용 경진대회 논문집
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    • 제4회(2015년)
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    • pp.343-346
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    • 2015
  • Ultra-thin body transistor is one of the emerging devices since it control leakage current flows through substrate. In addition, it can be operated by double gates, thus, its on/off current ratio is higher than conventional counterpart. In this paper, we design and investigate a CMOS inverter based on ultra-thin body MOSFETs to estimate its performance in real application. NEGF (non-equilibrium Green's function) method is used to obatain relationship between drain current and voltage. DC transfer is extracted from the relationship, and FO4 (fanout-of-4) propagation delay is reported as 5.1 ps estimated by a simple model.

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Oxide-Nitride-Oxide막을 게이트 절연막으로 사용하여 제조한 다결정실리콘 박막트랜지스티의 특성 (Properties of Poly-Si TFT's using Oxide-Nitride-Oxide Films as Gate Insulators)

  • 이인찬;마대영
    • 한국전기전자재료학회논문지
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    • 제16권12호
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    • pp.1065-1070
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    • 2003
  • HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.

오프셋 마스크를 이용하지 않는 새로운 자기 정합 폴리 실리콘 박막 트랜지스터 (A novel self-aligned offset gated polysilicon thin film transistor without an additional offset mask)

  • 민병혁;박철민;한민구
    • 전자공학회논문지A
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    • 제32A권5호
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    • pp.54-59
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    • 1995
  • We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.

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