• 제목/요약/키워드: On/off current ratio

검색결과 358건 처리시간 0.037초

선택적 레이저 어닐링을 이용하여 비정질 실리콘 오프셋을 갖는 Inverse Staggered 다결정 실리콘 박막 트랜지스터 (Inverse Sta99ered Poly-Si TFT with a-Si Offset formed by Selective Excimer Laser Annealing)

  • 박기찬;최권영;김천홍;한민구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1997년도 하계학술대회 논문집 C
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    • pp.1633-1635
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    • 1997
  • For AMLCD pixel switching device, poly-Si TFT has the advantage of high field effect mobility over a-Si TFT. However, it also has some disadvantage such as large leakage current and more masking steps. We propose a new Inverse Staggered poly-Si TFT with a-Si offset. We have fabricated the new device and verified high ON/OFF current ratio. The device has lower leakage current level than the conventional Inverse Staggered poly-Si TFT and the same number of masking steps compared with conventional a-Si TFT's.

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SQUID 센서 기반의 극저자장 자기공명 장치를 위한 사전자화코일 전류구동장치 개발 (Development of Prepolarization Coil Current Driver in SQUID Sensor-based Ultra Low-field Magnetic Resonance Apparatuses)

  • 황성민;김기웅;강찬석;이성주;이용호
    • Progress in Superconductivity
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    • 제13권2호
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    • pp.105-110
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    • 2011
  • SQUID sensor-based ultra low-field magnetic resonance apparatus with ${\mu}T$-level measurement field requires a strong prepolarization magnetic field ($B_p$) to magnetize its sample and obtain magnetic resonance signal with a high signal-to-noise ratio. This $B_p$ needs to be ramped down very quickly so that it does not interfere with signal acquisition which must take place before the sample magnetization relaxes off. A MOSFET switch-based $B_p$ coil driver has current ramp-down time ($t_{rd}$) that increases with $B_p$ current, which makes it unsuitable for driving high-field $B_p$ coil made of superconducting material. An energy cycling-type current driver has been developed for such a coil. This driver contains a storage capacitor inside a switch in IGBT-diode bridge configuration, which can manipulate how the capacitor is connected between the $B_p$ coil and its current source. The implemented circuit with 1.2 kV-tolerant devices was capable of driving 32 A current into a thick copper-wire solenoid $B_p$ coil with a 182 mm inner diameter, 0.23 H inductance, and 5.4 mT/A magnetic field-to-current ratio. The measured trd was 7.6 ms with a 160 ${\mu}F$ storage capacitor. trd was dependent only on the inductance of the coil and the capacitance of the driver capacitor. This driver is scalable to significantly higher current of superconducting $B_p$ coils without the $t_{rd}$ becoming unacceptably long with higher $B_p$ current.

AC 모듈형 태양광 모듈 집적형 컨버터를 위한 소프트 스위칭 DC-DC 컨버터 (Soft Switching DC-DC Converter for AC Module Type PV Module Integrated Converter)

  • 윤선재;김영호;정용채;원충연
    • 전력전자학회논문지
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    • 제18권3호
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    • pp.247-255
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    • 2013
  • In this paper, a soft switching DC-DC converter for AC module type photovoltaic (PV) module integrated converter is proposed. A push-pull converter is suitable for a low voltage PV AC module system because the step-up ratio of a high frequency transformer is high and the number of primary side switches is relatively small. However, the conventional push-pull converters do not have high efficiency because of high switching losses by hard switching and transformer losses (copper and iron losses) by high turns-ratio of the transformer. In the proposed converter, primary side switches are turned on at zero voltage switching (ZCS) condition and turned off at zero current switching (ZVS) condition through parallel resonance between secondary leakage inductance of the transformer and a resonant capacitor. Therefore the proposed push-pull converter decreases the switching loss using soft switching of the primary switches. Also, the turns-ratio of the transformer can be reduced by half using a voltage-doubler of secondary side. The theoretical analysis of the proposed converter is verified by simulation and experimental results.

철근 콘크리트 시험편의 철근방식에 관한 측정법 (Corrosion Measurements on Reinforcing Rebars in Reinforced Concrete Specimen)

  • 이강균;장지원;한기훈;정영수
    • 한국콘크리트학회:학술대회논문집
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    • 한국콘크리트학회 1997년도 가을 학술발표회 논문집
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    • pp.281-286
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    • 1997
  • Recent construction activities and maintenance of marine facilities have been accelerating to keep up with rapid economic growth in Korea. Marine concrete structures are exposed to salts an chloride from ocean environments. The corrosion of reinforcement steel caused by chloride-penetration into concrete may severely effect the durability of concrete structures. The objective of this research is to develop a durable concrete by investigating the corrosion resistance of various corrosion protection systems utilizing different water/cement ratio, silica fumes, corrosion inhibitors and etc. A tow-year verification test on various corrosion protection systems has been doing in the laboratory and at the seaside. Corrosion investigations on reinforcement steel are now under progress for more than 180 concrete specimen. Corrosion-related measurements include macrocell corrosion current, instant-off voltage between corroding and noncorroding reinforcement, chloride contents, the corroded surface areas on the reinforcement steel, and etc. A low level of corrosion is investigated on reinforcement steels in concrete specimen made with corrosion inhibitors or applied aqueous impregnating corrosion inhibitors into their surface, even though high chloride contents of concrete specimen.

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Role of a PVA layer During lithography of SnS2 thin Films Grown by Atomic layer Deposition

  • Ham, Giyul;Shin, Seokyoon;Lee, Juhyun;Lee, Namgue;Jeon, Hyeongtag
    • 반도체디스플레이기술학회지
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    • 제17권3호
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    • pp.41-45
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    • 2018
  • Two-dimensional (2D) materials have been studied extensively due to their excellent physical, chemical, and electrical properties. Among them, we report the material and device characteristics of tin disulfide ($SnS_2$). To apply $SnS_2$ as a channel layer in a transistor, $SnS_2$ channels were formed by a stripping method and a transfer method. The limitation of this method is that it is difficult to produce uniform device characteristics over a large area. Therefore, we directly deposited $SnS_2$ by atomic layer deposition (ALD) and then performed lithography. This method was able to produce devices with repeatable characteristics over a large area. However, the $SnS_2$ film was damaged by the acetone used as a photoresist (PR) developer during the lithography process, with the electrical properties of mobility of $2.6{\times}10^{-4}cm^2/Vs$, S.S. of 58.1 V/decade, and on/off current ratio of $1.8{\times}10^2$. These results are not suitable for advanced electronic devices. In this study, we analyzed the effect of acetone on $SnS_2$ and studied the device process to prevent such damage. Using polyvinyl alcohol (PVA) as a passivation layer during the lithography process, the electrical characteristics of the $SnS_2$ transistor had $2.11{\times}10^{-3}cm^2/Vs$ of mobility, 11.3 V/decade of S.S, and $2.5{\times}10^3$ of the on/off current ratio, which were 10x improvements to the $SnS_2$ transistor fabricated by the conventional method.

Offset 구조 Poly-Si TFT의 Negative Bias Stress 효과 (Negative Bias Stress Effect with Offset Structure in Poly-Si TFT's)

  • 이제혁;변문기;임동규;조봉희;김영호
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1998년도 추계학술대회 논문집
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    • pp.141-144
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    • 1998
  • The electrical characteristics of poly-Si TFT's with offset structure by negative bias stress are systematically investigated as a function of offset length. The changes of electrical characteristics, V$\_$th/, off-current, on/off ratio, in the offset structured poly-Si TFT's are smaller than that of the conventional structured poly-Si TFT's under the stress condition (V$\_$ds/=20V, V$\_$gs/=-20V). It is found that the hot carrier effect by negative bias stress is suppressed by the offset structured poly-Si TFT's because the local electric field near the drain region is decreased by offset region.

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The Electrical Characteristics of Low-Temperature Poly-Si Thin-Film Transistors by Different Crystallization Methods

  • 김문수;장경수;이준신
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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    • pp.287.1-287.1
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    • 2014
  • 본 연구에서는 현재 디스플레이에서 가장 널리 이용되는 저온 polycrystalline silicon (poly-Si)의 결정화 방법에 따른 thin-film transistor (TFT)의 전기적 특성을 분석하였다. 분석에 이용된 결정화 방식은 Excimer Laser Annealing (ELA)와 Metal Induced Crystallization (MIC)이다. ELA와 MIC TFTs의 전기적 특성 측정을 통한 분석결과 ELA와 MIC poly-Si TFTs의 전기적 특성 [field-effect mobility (${\mu}_{FE}$), on/off current ratio ($I_{ON}/I_{OFF}$), sub-threshold swing (SS)]은 큰 차이는 없지만, ELA를 이용한 poly-Si TFT의 전기적 특성이 조금 우수하다. 하지만, MIC poly-Si TFT의 경우 threshold voltage ($V_{TH}$)가 0V에 보다 가까울 뿐만 아니라, 전기적 스트레스를 통한 신뢰성 확인 시 ELA poly-Si TFT보다 조금 더 안정적이다. 이는 ELA의 경우 좁은 면에 선형 레이저 빔으로 조사하면서 생기는 hill-lock의 영향으로 표면이 거칠고 균일하지 못하여 바이어스 인가시 생기는 문제이다. 또한 MIC는 금속 촉매를 이용해 결정립 경계를 확장하고 결정 크기를 키워 대면적화에 유리하다. Thermal Stress에서는 (from 293K to 373K) TFT에 점차 높은 온도를 가하자 MIC poly-Si TFT의 경우 off 상태에서 누설 전류 값이 증가하며 열에 민감한 반응을 보이는 것을 확인하였다.

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Bi-directional Two Terminal Switching Device based on SiGe for Spin Transfer Torque (STT) MRAM

  • Yang, Hyung-Jun;Kil, Gyu-Hyun;Lee, Sung-Hyun;Song, Yun-Heub
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.385-385
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    • 2012
  • A two terminal N+/P/N+ junction device to replace the conventional selective transistor was studied as a bilateral switching device for spin transfer torque (STT) MRAM based on 3D device simulation. An N+/P/N+ junction structure with $30{\times}30nm$ area requires bi-directional current flow enough to write a data by a drain induced barrier lowering (DIBL) under a reverse bias at N+/P (or P/N+ junction), and high current on/off ratio of 106. The SiGe materials are widely used in hetero-junction bipolar transistors, bipolar compensation metal-oxide semiconductors (BiCMOS) since the band gap of SiGe materials can be controlled by changing the fraction and the strain epilayers, and the drift mobility is increased with the increasing Ge content. In this work, N+/P/N+ SiGe material based junction provides that drive current is increased from 40 to $130{\mu}A$ by increased Ge content from 10~80%. When Ge content is about 20%, the drive current density of SiGe device substantially increased to 2~3 times better than Si-based junction device in case of 28 nm P length, which is sufficient current to operation of STT-MRAM.

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N형 유기물질을 이용한 세로형 유기 발광트랜지스터의 제작 및 특성에 관한 연구 (Characteristics and Fabrication of Vertical Type Organic Light Emitting Transistors Using n-Type Organic Materials)

  • 오세용;김희정;장경미
    • 폴리머
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    • 제30권3호
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    • pp.253-258
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    • 2006
  • 4 종류의 n형 유기 반도체 물질 F16CuPC, NTCDA, PTCDA, PTCDI C-8을 사용하여 ITO/n형 활성물질/Al gate/n형 활성물질/Al으로 구성되는 세로형 유기 박막트랜지스터를 제작하였다. 캐리어 이동도의 차이를 갖는 유기 물질의 종류와 유기 박막층의 두께 조절에 따른 유기 박막트랜지스터의 전류전압(I-V) 특성 및 전류의 온오프비에 미치는 영향을 조사하였다. PTCDI C-8을 사용한 세로형 유기 박막트랜지스터에서 낮은 구동전압과 높은 스위칭 특성을 보였다. ITO/PEDOT-PSS/P3HT/F16CuPc/Al gate/F16CuPc/Al으로 구성되는 발광트랜지스터를 제작하였고, 20 V에서 최고 0.054의 양자 효율을 나타내었다.

An Organic Electrophosphorescent Device Driven by All-Organic Thin-Film Transistor using Polymeric Gate Insulator

  • Pyo, S.W.;Shim, J.H.;Kim, Y.K.
    • Journal of Information Display
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    • 제4권2호
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    • pp.1-6
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    • 2003
  • In this paper, we demonstrate that the organic electrophosphorescent device is driven by the organic thin film transistor with spin-coated photoacryl gate insulator. It was found that electrical output characteristics in our organic thin film transistors using the staggered-inverted top-contact structure showed the non-saturated slope in the saturation region and the sub-threshold nonlinearity in the triode region, where we obtained the maximum power luminance that was about 90 $cd/m^2$. Field effect mobility, threshold voltage, and on-off current ratio in 0.45 ${\mu}m$ thick gate dielectric layer were 0.17 $cm^2/Vs$, -7 V, and $10^6$ , respectively. In order to form polyimide as a gate insulator, vapor deposition polymerization process was also introduced instead of spin-coating process, where polyimide film was co-deposited by high-vacuum thermal evaporation from 4,4'-oxydiphthalic anhydride (ODPA) and 4,4'-oxydianiline (ODA) and cured at 150${\sqsubset}$for 1hr. It was also found that field effect mobility, threshold voltage, on-off current ratio, and sub-threshold slope with 0.45 ${\mu}m$ thick gate dielectric films were 0.134 $cm^2/Vs$, -7 V, and $10^6$ A/A, and 1 V/decade, respectively.