• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2011년도 춘계학술발표대회 논문집
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• pp.293-298
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• 2011

The most widely used method to form an electrode in industrial solar cells are screen printing. Screen printing is characterized by a relatively simple and well-known production sequence with high throughput rates. However the method is difficult to implement a fine line width of high-efficiency solar cells can not be made. The open circuit voltage(Voc) and the short circuit current density(Jsc) and fill factor(FF) need to be further improved to increase the efficiency of silicon solar cells. In this study, gravure offset printing method using the multicrystalline-silicon solar cells were fabricated. Gravure off-set printing method which can print the fine line width of finger electrode can have the ability reduce the shaded area and increase the Jsc. Moreover it can make a high aspect ratio thereby series resistance is reduced and FF is increased. Approximately $50{\mu}m$ line width with $35{\mu}m$ height was achieved. The efficiency of gravure off set was 0.7% higher compare to that of scree printing method.

• KIEE International Transactions on Power Engineering
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• 제5A권2호
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• pp.138-143
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• 2005

During faults, the voltage and current signals available to the relay are affected by the decaying dc component and harmonics. In order to make appropriate and accurate decisions, most of the relaying algorithms require the fundamental frequency phasor information that is immune to decaying dc effect and harmonics. The conventional Fourier ph as or estimation algorithm is affected by the presence of decaying-exponential transients in the fault signal. This paper presents a modified Fourier algorithm, which effectively eliminates the decaying dc component and the harmonics present in the fault signal. The decaying dc parameters are estimated by means of an out-of-band filtering technique. The decaying dc offset and harmonics are removed by means of a simple computational procedure that involves the design of two sets of Orthogonal digital OFT filters tuned at different frequencies and by creating three off-line look-up tables. The technique was tested for different decay rates of the decaying dc component. It was also compared with the conventional mimic plus the full cycle OFT algorithm. The results indicate that the proposed technique has a faster convergence to the desired value compared to the conventional mimic plus OFT algorithms over a wide range of decay rates. In all cases, the convergence to the desired value was achieved within one cycle of the power system frequency.

• ETRI Journal
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• 제33권3호
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• pp.366-373
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• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.83-87
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• 2004

Phase noise performance and current consumption of Radio Frequency (RF) Voltage-Controlled Oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor-capacitor (LC) tank. Because the Q-factor of LC tank is determined by on-chip spiral inductor, we designed, analyzed, and modeled on-chip differential inductor to enhance differential Q-factor, reduce current consumption and save silicon area. The simulated inductance is 3.3 nH and Q-factor is 15 at 2 GHz. Self-resonance frequency is as high as 13 GHz. To verify its use to RF applications, we designed 2 GHz differential LC VCO. The measurement result of phase noise is -112 dBc/Hz at an offset frequency of 100 kHz from a 2GHz carrier frequency. Tuning range is about 500 MHz (25%), and current consumption varies from 5mA to 8.4 mA using bias control technique. Implemented in $0.35-{\mu}m$ SiGe BiCMOS technology, the VCO occupies $400\;um{\times}800\;um$ of silicon area.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.503-504
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• 2006

This paper presents the design and fabrication of a LC voltage-controlled oscillator (VCO) using 1-poly 6-metal mixed signal CMOS process. To obtain the high-quality factor inductor in LC resonator, patterned-ground shields (PGS) is placed under the symmetric inductor to reduce the effect from image current of resistive Si substrate. Moreover, due to the incapability of using thick top metal layer of which the thickness is over $2{\mu}m$, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via materials along the metal traces is adopted. The circuit operated from 2.63 GHz to 3.09 GHz tuned by accumulation-mode MOS varactor. The corresponding tuning range was 460 MHz. The measured phase noise was -115 dBc/Hz @ 1MHz offset at 2.63 GHz carrier frequency and the current consumption and the corresponding power consumption were about 2.6 mA and 4.68 mW respectively.

• Journal of Power Electronics
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• 제9권4호
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• pp.654-666
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• 2009

Direct torque control (DTC) of induction machines (IM) is a well-known strategy of these drives control which has a fast dynamic and a good tracking response. In this paper a nonlinear DTC of speed sensorless IM drives is presented which is based on input-output feedback linearization control theory. The IM model includes iron losses using a speed dependent shunt resistance which is determined through some effective experiments. A stator flux vector is estimated through a simple integrator based on stator voltage equations in the stationary frame. A novel method is introduced for DC offset compensation which is a major problem of AC machines, especially at low speeds. Rotor speed is also determined using a rotor flux sliding-mode (SM) observer which is capable of rotor flux space vector and rotor speed simultaneous estimation. In addition, stator and rotor resistances are estimated using a simple but effective recursive least squares (RLS) method combined with the so-called SM observer. The proposed control idea is experimentally implemented in real time using a FPGA board synchronized with a personal computer (PC). Simulation and experimental results are presented to show the capability and validity of the proposed control method.

• ETRI Journal
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• 제33권2호
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• pp.201-209
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• 2011

This paper presents a wide-band fine-resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three-step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.

• Journal of electromagnetic engineering and science
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• 제6권1호
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• pp.30-35
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• 2006

This paper describes fully integrated low phase noise MMIC voltage controlled oscillators(VCOs). The Asymmetrical Inductance Tank VCO(AIT-VCO), which optimize the shortcoming of the previous tank's inductance optimization approach, has lower phase noise performance due to achieving higher equivalent parallel resistance and Q value of the tank. This VCO features an output power signal in the range of - 11.53 dBm and a tuning range of 261 MHz or 15.2 % of its operating frequency. This VCO exhibits a phase noise of - 117.3 dBc/Hz at a frequency offset of 100 kHz from carrier. A phase noise reduction of 15 dB was achieved relative to only one spiral inductor. The AIT-VCO achieved low very low figure of merit of -184.6 dBc/Hz. The die area, including buffers and bond pads, is $0.9{\times}0.9mm^2$.

• 한국전자파학회논문지
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• 제18권5호
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• pp.511-521
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• 2007

본 논문에서는 복합 소형화된 Ka-대역 주파수 합성기 모듈을 제작하였다. 본 논문을 통하여 소형화 구성시 배치 방법과 체계적인 검증 방법을 제시하였다. 제작된 주파수 합성기는 X-대역 전압 제어 발진기(VCO: Voltage Controlled Oscillator)의 주파수를 3체배하여 구성하였으며, 제작된 모듈은 500 MHz 주파수 가변 범위와 약 14 dBm의 출력 전력, 그리고 100 kHz 오프셋 주파수에서 -96.17 dBc/Hz의 위상 잡음 특성을 보여주고 있다.

• 전기학회논문지
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• 제60권2호
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.