• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.98-106
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• 2009

This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.22-26
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• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.117-124
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• 2009

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

• Economic and Environmental Geology
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• v.27 no.1
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• pp.65-80
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• 1994

The Tertiary $Ch{\check{o}}ngja$ basin is located in the southeastern coastal area of the Korean Peninsula. It is a lozenge shaped fault-bounded basin with circa $5{\times}5km$ areal extent, isolated from other Tertiary basins by the Cretaceous Ulsan Formation in-between. The northwestern boundary of the basin is a domino/listric type normal fault trending $N30^{\circ}E$, whereas its southwestern boundary is a dextral strike-slip fault (trending $N20^{\circ}W$) with a lateral offset of more than 1 km. The basin is bounded by the East Sea on the eastern margin. Basin-fills consist of extrusive volcanic rock (Tangsa Andesites) of Early Miocene (16~22 Ma in radiometric age), unconsolidated fluviatile conglomerate (Kangdong Formation) and shallow brackish-water sandstone ($Sinhy{\check{o}}n$ Formation). The latter yields abundant Vicarya-Anadara molluscan fossils of early Middle Miocene age. The Tertiary strata become younger toward the northwestern boundary-fault of the basin, showing a zonal distribution pattern parallel to the fault: the younger sedimentary formations occupy a narrow zone of 2 km width along the northwestern boundary-fault, whereas the older Tangsa Andesites underlie them unconformably in the eastern and southeastern portions of the basin. The strata in the basin, including the Tangsa Andesites, are tilted (about $20^{\circ}$) toward the northwestern boundary-fault Sedimentary strata thicken toward the boundary-fault, forming a wedge shaped half-graben structure. A number of small-scale syndepositional normal growth faults and graben structures are observed in the sedimentary strata. These extensional structures have the same trend as the normal northwestern boundary-fault which we interpret as a pull-apart detachment fault. These characteristics imply persistent extension during the basin evolution, caused by a NW-SE directed tensional force. The $Ch{\check{o}}ngja$ basin is, thus, a kind of syndepositional tectonic basin evolved in a strike-slip (pull-apart) regime. The latter was caused by a dextral simple shear associated with the NNW-SSE opening of the East Sea. In view of the fact that the normal growth faults do not cut through the uppermost portion of the youngest $Sinhy{\check{o}}n$ Formation, it is inferred that the tensional force came to be inactive in the early Middle Miocene. This is coincident in timing with the termination of the East Sea opening (15 Ma).

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.126-142
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• 2016

This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.758-765
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• 2018

This paper presents a 24-GHz frequency-modulated continuous wave(FMCW) radar transceiver with two Rx and one Tx channels in 65-nm complementary metal-oxide-semiconductor(CMOS) process and implemented it on a radar system using the developed transceiver chip. The transceiver chip includes a $14{\times}$ frequency multiplier, low-noise amplifier, down-conversion mixer, and power amplifier(PA). The transmitter achieves >10 dBm output power from 23.8 to 24.36 GHz and the phase noise is -97.3 GHz/Hz at a 1-MHz offset. The receiver achieves 25.2 dB conversion gain and output $P_{1dB}$ of -31.7 dBm. The transceiver consumes 295 mW of power and occupies an area of $1.63{\times}1.6mm^2$. The radar system is fabricated on a low-loss Duroid printed circuit board(PCB) stacked on the low-cost FR4 PCBs. The chip and antenna are placed on the Duroid PCB with interconnects and bias, gain blocks and FMCW signal-generating circuitry are mounted on the FR4 PCB. The transmit antenna is a $4{\times}4$ patch array with 14.76 dBi gain and receiving antennas are two $4{\times}2$ patch antennas with a gain of 11.77 dBi. The operation of the radar is evaluated and confirmed by detecting the range and azimuthal angle of the corner reflectors.

• Journal of the Korean Institute of Landscape Architecture
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• v.33 no.6 s.113
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• pp.98-108
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• 2006

The climate of urban area is an unstable type with considerable seasonal variation in precipitation wind speed, and temperature and it grows worse. Besides, ozone is a serious air pollutant in most of large cities. So worldwide, some of large cities are investing in forestry options to offset their climate problems, but lack of information has hindered comparisons of urban un cost effectiveness to other options. This research intends to study the economic benefits of tree shading of 19 parking lots in UCD campus. The economic benefits of tree shading are air conditioning savings, air quality, stormwater run-off, and other benefits. Especially, this study focuses how much the economic benefit of parking lot shading has been increased from 1995 to 2003 year by aerophoto. Some data on dimensions of parking lots and the number, size, tree species, and location of trees around each parking lot was inventoried. Two aerophotos(1995,2003) were used in order to analyze the increasement of tree canopy in 19 parking lots for 8 years. However, increasing coverage of trees and managing them for healthy growth would not be sufficient for avoiding adverse impacts by future climate change. Additional measures should be followed such as an increase of energy use efficiency and development of substitute energy. For example, coverage of trees help to save cooling energy by blocking solar radiation reaching parking cars and building structures through shading, and creating cool micro-climates through evapotranspiration. They also reduce heating demand by decreasing air infiltration and heat conduction out of the interior of buildings. Proper arrangement of vegetation over the parking lots can reduce cooling and heating costs. So proper planting design around hard space paving including species selection and location can significantly save cooling and heating energy. And a reduction in car and building's heating and cooling costs results in the reduction in energy demand which causes to emissions of air pollutants. Total increased tree canopy from 1995 to 2003 is $8,470.45m^2$ and the economic benefits is US$ 5,282.10. The economic benefit of one tree has been US$ 7.21 for 8 years. And an annually increased benefit is US$ 0.9 per a tree. If this kind of study is applied to studying the economic benefits of tree canopy in parking lots of Korea, it could result in guidelines of tree planting of parking lots. Because the trees selected for planting in parking lots were not suitable for an environment, the guidelines should contain a recommended list of trees. The guidelines should propose the shading percentage of parking lot when we plan a parking lot and contain the maintenance of trees in order to maximize the economic benefits of tree canopy.