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Quantitative Analysis of Glottal Cycles According to Frequency and Intensity Variations in Normal Speakers (발성의 강도와 주파수 변화에 따른 성대 움직임의 정량적 분석)

  • Young-Ik Son;Kyungah Lee;Jun-Sun Ryu;Chung-Hwan Baek
    • Journal of the Korean Society of Laryngology, Phoniatrics and Logopedics
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    • v.8 no.1
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    • pp.5-11
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    • 1997
  • To set up an objective basis for the evaluation of the stroboscopic findings, video-strobolaryngoscopic images of vocal fold vibration in 5 female and 5 male normal speakers were analyzed using an image analysis computer program called KSIP(Kay Storoboscopy Image Processing, Kay Elemetrics Corp., NJ, USA). Four consecutive vibratory cycles were compared in comfortable, louder, high-pitched /ee/ phonation for every subject. findings mostly replicated earlier studies including glottal chinks which were observed in most female speakers throughout the cycles and clear distinction between female and male speakers in their vibratory patterns as well as intensity and frequency-re-lated differences. However, there were some findings incompatible with those from previous studies which may be attributable to technical problems. This study may provide an objective basis of the stroboscopic findings such as image shape, amplitude, area, and their changes according to frequency and intensity variations. We anticipate that funker study with larger samples ran provide an objective criteria for normal vibratory characteristics of the laryngostro-boscopic findings.

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Artificial Sea Ice Increasing to Mitigate Global Warming (지구 온난화 경감을 위한 인공해빙증가)

  • Byun, Hi-Ryong;Park, Chang-Kyun
    • Journal of the Korean earth science society
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    • v.36 no.6
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    • pp.501-511
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    • 2015
  • This study suggests a method of alleviating global warming by the increase of the Earth surface albedo through Artificial Sea ice Increasing (ASI) over the Available Freezing Areas (AFA). The method is developed based on the fact that the large sea surface area in or near the Arctic and the Antarctic has no ice even though both water and air temperatures are below zero and the artificial sea ice generation is thus available. The mean energy of $0.85Wm^{-2}$, which was suspected of adding to the earth by the global warming effect was calculated to offset at once when the sea ice area about $4.09{\times}10^6km^2$ was additionally increased. In addition, three techniques for producing ice plates on the sea surface (using ships, installation apparatus, and floating matter such as Green Cell Foam) for ASI were proposed. According to the result of simple analysis using the energy balance model, when ASI was maximally operated only for 3 months (September, October, and November) over AFA, it is expected that the annual mean temperature of earth surface would be decreased about $0.11^{\circ}C$ in the following year. On the other hand, in case of generating the artificial sea ice in all four seasons, a risk of triggering snowball earth was detected.

A 14b 100MS/s $3.4mm^2$ 145mW 0.18um CMOS Pipeline A/D Converter (14b 100MS/s $3.4mm^2$ 145mW 0.18un CMOS 파이프라인 A/D 변환기)

  • Kim Young-Ju;Park Yong-Hyun;Yoo Si-Wook;Kim Yong-Woo;Lee Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.5 s.347
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    • pp.54-63
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    • 2006
  • This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

Seismic Refraction Analysis to Estimate the Depth to the Bedrock: Case Study (기반암 깊이 도출을 위한 굴절법 탄성파 자료 분석: 사례연구)

  • Lee, Doo-Sung
    • Geophysics and Geophysical Exploration
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    • v.8 no.4
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    • pp.237-242
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    • 2005
  • A seismic refraction study in estimation of depth to the bedrock demonstrates that 1) the average velocity in the medium is about 250 m/s in the surface layer (< 4 m), 2,500 m/s in the weathered formation, and greater than 3,000 m/s in the bedrock, 2) the depth to the deepest reflector assumed to be the bedrock is about 17 m; however, according to the cores collected in a borehole in study area, the bedrock (granite) occurred at depth 25 m, 3) according to the density and velocity logging, at depth 17 m, a measurable velocity and density increase are observed, and 4) the velocity of the weathered formation is relatively high and therefore, the acquisition offsets ($70{\sim}80m$) are turned out not to be long enough to record the refracted signal from the bedrock at depth 25 m as first arrivals.

A CMOS Analog Front End for a WPAN Zero-IF Receiver

  • Moon, Yeon-Kug;Seo, Hae-Moon;Park, Yong-Kuk;Won, Kwang-Ho;Lim, Seung-Ok;Kang, Jeong-Hoon;Park, Young-Choong;Yoon, Myung-Hyun;Yoo, June-Jae;Kim, Seong-Dong
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.769-772
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    • 2005
  • This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

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A $2{\sim}6GHz$ Wide-band CMOS Frequency Synthesizer With Single LC-tank VCO (싱글 LC-탱크 전압제어발진기를 갖는 $2{\sim}6GHz$의 광대역 CMOS 주파수 합성기)

  • Jeong, Chan-Young;Yoo, Chang-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.9
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    • pp.74-80
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    • 2009
  • This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

Design of a Digitally Controlled LC Oscillator Using DAC for WLAN Applications (WLAN 응용을 위한 DAC를 이용한 Digitally Controlled LC Oscillator 설계)

  • Seo, Hee-Teak;Park, Jun-Ho;Kwon, Duck-Ki;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.15 no.1
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    • pp.29-36
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    • 2011
  • Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

A Study on Feed Rate Characteristics of Motor-driven Cylinder Lubricator with Electronic Control Quill in a Large Two-stroke Diesel Engine (대형 2행정 디젤기관에 있어서 전자제어 퀼 부착 모터구동 실린더 주유기의 송출유량 특성에 관한 연구)

  • Bae, Myung-Whan;Jung, Hwa;Jung, Yeun-Hak;Kim, In-Deok;Kang, Chang-Ho
    • Transactions of the Korean Society of Automotive Engineers
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    • v.15 no.6
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    • pp.1-8
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    • 2007
  • Minimizing the cylinder wear and the consumption rate of cylinder oil in a large two-stroke marine diesel engine is of great economic importance. In Korea, authors first developed a motor-driven cylinder lubricator for a Wartsila Switzerland large two-stroke diesel engine. The characteristic of the developed product is that can control automatically the oil feed rate with a load fluctuation by the motor drive and the offset cam. For manufacturing the reliable and useful products, however, it is necessary to investigate further characteristics and to improve performances as a cylinder lubricator. In this study, the effects of pump motor speed, plunger stroke and cylinder back pressure on oil feed rate, maximum discharge and delivery pressures are experimentally investigated by using the electronically controlled quill injection system and distributer in the developed cylinder lubricator. It is found that the oil feed rates of electronic control and mechanical type quills with the in-cylinder back pressure are differently characterized by the role of accumulator, the viscous resistance of contact area, etc. It can be also shown that the maximum discharge pressure of the electronic control quill is lower than the mechanical type one but the maximum discharge pressure difference of two types decreased as plunger stroke is small, and the maximum delivery pressures of two types increased as plunger stroke, motor speed and back pressure are elevated but the maximum delivery pressure of mechanical type is higher than the one of electronic control type.

A 10-bit 10-MS/s 0.18-㎛ CMOS Asynchronous SAR ADC with split-capacitor based differential DAC (분할-커패시터 기반의 차동 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 0.18-㎛ CMOS 비동기 축차근사형 아날로그-디지털 변환기)

  • Jeong, Yeon-Ho;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.2
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    • pp.414-422
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    • 2013
  • This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

The Design of Dual Phase LNB for DBS Receiving (DBS 수신을 위한 Dual Phase LNB 설계)

  • Lim, Yun-Doo;Ko, Bong-Jin
    • Journal of Advanced Navigation Technology
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    • v.6 no.3
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    • pp.188-194
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    • 2002
  • DBS is utilized as very useful media in information-oriented society because it covers wide service area and provide high quality services. But DBS needs skill that can receive DBS signal at move. In this paper, it is considered a development of a device to receive DBS and design of a low noise downconverter that use tracking antenna to receive DBS at mobiles unit and ships which navigate in Korea peninsula coast. The structure of dual phase LNB is composed of LNA, BPF, oscillator, mixer, and IF amplifier. And for the position tracking, two input-output phase performed in phase. Measured results showed good performance that with respect to input signal 11.7 GHz~12.2 GHz, noise figure is 0.87 dBmax and conversion gain 62 dB, temperature characterization ${\pm}400$ kHz in respect to - 30 to $60^{\circ}C$, and phase noise -101 dBc/Hz in respect to offset 100 kHz.

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