• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
• /
• pp.605-608
• /
• 2002

This paper proposes a real-time wall charge measurement circuit for three-electrode AC PDP. It includes a charge-compensation network, current-integrating capacitors, initializing switches, and an op-amp. With this equipment, we measure the wall charge variations for the effects of sustain voltage, sustain pulse width, sustain frequency, and neighboring cells.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
• /
• pp.581-584
• /
• 2003

The phase differences and noise signals are in general serious on output of a instrumentation amplifier for signal conditioning of a sensor driven at high frequency due to a time-varying input signal. In this study, we get the better amplification and S/N ratio using the rectified signal for the input of instrumentation amplifier. This driving circuits were designed and constructed by OrCAD and laboratory PCB process. All of the elements used on the circuit including highly speedy OP-Amp. was SMD type and the MI sensor was fabricated by meander-patterned amorphous ribbon. The output sensitivity of this circuit was $105.3mV/V{\cdot}Oe$. That's why this driving circuit is good at detection of fine magnetic field.

• 한국산학기술학회논문지
• /
• 제13권1호
• /
• pp.311-316
• /
• 2012

본 논문에서는 공학적 응용을 위한 로렌츠 카오스 시스템을 연산증폭기, 곱셈기 등을 이용하여 전자회로로 설계하였다. 시간파형, 위상특성 등 여러 가지 카오스 동적특성 등을 PSPICE 모의실험을 통하여 파악하였다. 저항값의 변화를 통하여 카오스 특성을 얻기 위한 최적화 된 회로 파라미터를 구하였으며, 각 저항값의 변화에 따른 시간파형 특성 및 위상 특성을 구하였다.

• 동의생리병리학회지
• /
• 제28권1호
• /
• pp.59-62
• /
• 2014

Glucose uptake plays a pivotal role in maintaining whole body glucose homeostasis in adipocytes and skeletal muscles. In the present study we have shown that Fructus Piperis Longi Extracts (FPLE) can stimulate glucose uptake in OP9 adipocytes. The increasing effects of FPLE on glucose uptake were inhibited by compound C pretreatment, which means that the glucose uptake effects by FPLE were carried out by AMP-activated protein kinase (AMPK) activation. Further studies revealed that FPLE stimulated glucose transport occurs through a mechanism involving extracellular signal-regulated kinase (ERK1/2) activation.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 1995년도 춘계학술대회 논문집
• /
• pp.383-388
• /
• 1995

The ARC light has been measured using photo-detect system under different TIG welding condition. Light detect system consists of photo diode, ND Filter, OP Amp. A/D convertor and PC. The purpose of this experiment is to show the relationship between ARC light and process variables such as welding current, torch travel speed, etc. The results can be applied to estimate the condition of welding process and the quality of welding products. The signal of ARC light has periodic patterns in good TIG welding condition whereas in abnormal condition the signal has different pattern. Amount of Ar shielding gas and distance from electrode to specimen affect the signal pattern significantly.

• 한국통신학회논문지
• /
• 제22권7호
• /
• pp.1579-1589
• /
• 1997

This paper introduces a monolithic chip 3.3V high-performance continuous-tune filter used in a CDP that can reconstruct the PDM or PWM signal output of a .SIGMA..DELTA. D/A converter. We also mentioned an active RC filter structure and filter order satisfying high-linearity and the design specification. In desigining the OP-AMP, using a structure that accepts some distortion we could reduce the chip area, and reducing the DC path using a new biascircuit gave us better power performance. The designed.SIGMA..DELTA. D/A converter post-processing filter does its smoothering operations and reconstructs the data without reducing the performance of the system.

• 한국컴퓨터정보학회논문지
• /
• 제7권2호
• /
• pp.68-72
• /
• 2002

본 논문에서는 OTA의 원리와 기본응용에 대하여 연구하였다. 또한 OTA를 응용하여 3개의 입력과 1개의 출력을 갖는 2차 필터를 설계하여 3입력중의 각각 1입력만을 사용한다면 각각 저역통과, 중역통과, 고역통과 필터의 특성을 얻을 수 있었다. 컴퓨터 시뮬레이션 결과 이론값과 잘 일치하였으며, 이 필터는 저왜곡, 고주파 특성을 갖는 통신 시스템의 응용에 사용될수 있다.

• 제어로봇시스템학회논문지
• /
• 제7권2호
• /
• pp.102-108
• /
• 2001

In this paper, an active noise controller for a communication headset was designed. In a communication headset, there exist information signals such as voices from the end for the communication line as well as also, undesirable noises with are induced by external noise sources such as engine noises. Therefore, it is necessary to reduce the external noises for clear hearing of the communication signals. This problem was solved by robust H(sub)$\infty$ controller to reduce noise and a compensator for information signals The designed controller was implemented using TMS320C31 DSP Op-amp, and several experiments were performed to verify its performance. The results showed that the controller reduces the undesirable noises sufficiently, while communication signals are not reduced.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.627-628
• /
• 2006

A low-voltage switched-capacitor $2^{nd}$-order $\Sigma\Delta$ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the $\Sigma\Delta$ loop. These features greatly relax the DC gain and output swing requirements for Op-Amp in the low-voltage $\Sigma\Delta$ modulator. Implemented by a 0.18-${\mu}m$ CMOS technology, the $\Sigma\Delta$ modulator satisfies performance requirements for WCDMA and CDMA2000 standards.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권3호
• /
• pp.319-329
• /
• 2016

High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.