• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.209-220
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• 2014

Compressive Sensing (CS) is a new signal acquisition paradigm which enables sampling under Nyquist rate for a special kind of signal called sparse signal. There are plenty of CS recovery methods but their performance are still challenging, especially at a low sub-rate. For CS recovery of natural images, regularizations exploiting some prior information can be used in order to enhance CS performance. In this context, this paper addresses improving quality of reconstructed natural images based on Dantzig selector and smooth filters (i.e., Gaussian filter and nonlocal means filter) to generate a new regularization called smooth residual error regularization. Moreover, total variation has been proved for its success in preserving edge objects and boundary of reconstructed images. Therefore, effectiveness of the proposed regularization is verified by experimenting it using augmented Lagrangian total variation minimization. This framework is considered as a new CS recovery seeking smoothness in residual images. Experimental results demonstrate significant improvement of the proposed framework over some other CS recoveries both in subjective and objective qualities. In the best case, our algorithm gains up to 9.14 dB compared with the CS recovery using Bayesian framework.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.16-24
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• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Journal of radiological science and technology
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• v.39 no.3
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• pp.415-420
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• 2016

The purpose of this study was to evaluation of the performance characteristic for mammography by using edge device that mammography equipment improves essential in the correct diagnosis for the maintenance. We measured the modulation transfer function (MTF), the noise power spectrum (NPS), and the detective quantum efficiency (DQE) using the 61267 RQA-M2 based on commission standard international electro-technical commission (IEC). As a results, spatial resolution of elenia demensions tomo and lorad selenia mammography were maintained at $10mm^{-1}$ and NPS and DQE including the low nyquist frequency indicated to $6.0mm^{-1}$. Therefore, regulary QA of mammography system should be necessary. This study can be contribute to evaluate QA for performance characteristic of mammography of DDR system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Korean Journal of Optics and Photonics
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• v.29 no.4
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• pp.166-172
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• 2018

In this paper, we propose a new method to predict a mirror's surface deformation due to the stress of moisture release by a coating in the environment of outer space. We measured the surface deformation of circular samples 50 mm in diameter and 1.03 mm thick, using an interferometer. The results were analyzed using Zernike fringe polynomials. The coating stress caused by moisture release was calculated to be 152.7 MPa. This value was applied to an analytic model of a 1.25 mm thickness sample mirror, confirming that the change of surface deformation could be predicted within the standard deviation of the measurement result ($78.9{\pm}5.9nm$). Using this methodology, we predicted the surface deformation of 600 mm hyperbolic mirror for the Compact Advanced Satellite, which will be launched in 2019. The result is only $2.005{\mu}m$ of focal shift, leading to 2.3% degradation of modulation transfer function (MTF) at the Nyquist frequency, which satisfies the requirement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of the Korea institute for structural maintenance and inspection
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• v.24 no.3
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• pp.87-95
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• 2020

As an experimental study on the corrosion behavior of steel materials to which ATMS method using EIS was applied in concrete, immersion of Ca(OH)₂ saturated aqueous solution and NaCl aqueous solution simulating the environment inside concrete The corrosion behavior was tested. The equivalent circuit was derived through the analysis of the Nyquist plot, and the interfacial resistance and the polarization resistance of the Ca(OH)₂ aqueous solution were compared, and Al ATMS was the best interfacial resistance and Zn ATMS was the best polarization resistance. After burying ATMS steel material of cement mortar, the initial immersion impedance measurement value was the highest in the Zn ATMS test body in the impedance measurement by the immersion time by immersing it in the NaCl aqueous solution. Al ATMS test piece has the highest impedance and is highly reliable. This is because Al, which has a high ionization tendency, is continuously oxidized in a strong alkaline environment to form a film and protect the steel from permeation of chlorine ions.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.4
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• pp.509-518
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• 2014

Though various techniques have been studied as a way of adjusting parameters of PID controllers, no perfect method of determining parameters is available to date. Especially the deign of PID controller for unstable processes with dead time(UPWDT) is even more difficult due to various reasons. Generally the existing design procedures for UPWDT involve deriving formulas to meet gain and phase margin specifications, or using inner loop to stabilize UPWDT before applying PID controller. In this paper, the dual-input describing function(DIDF) method is proposed, by which the performance and robustness of the closed-loop system can be improved. The method is based on moving the critical point (-1+j0) of Nyquist stability to a new position arbitrarily selected on the complex plane. This can be done by determining appropriate coefficients of the DIDF. As a result, we can easily determine parameters of PID-type controller by using existing conventional tuning methods for stable or unstable systems. Simulation results are included to show the effectiveness of the proposed method.